NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 88

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.2.7
88
PAM6 - Programmable Attribute Map Register 6
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0E 8000h -0E FFFFh.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
1:0
7:6
5:4
3:2
1:0
Bit
Bit
Attr
Attr
RW
RW
RW
RV
RV
16
0
5Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
5Fh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
00
00
00
00
00
LOENABLE5: 0E0000-0E3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E0000-0E3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
ESIENABLE6: 0EC000-0DFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0EC000-0DFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE6: 0E8000-0EBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E8000-0EBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Description
Description
Register Description