NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 90

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.2.9
3.8.2.10
90
EXSMRC - Extended System Management RAM Control Register
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MByte.
EXSMRTOP - Extended System Management RAM Top Register
This register defines the location of the Extended (TSEG) SMM range by defining the
top of the TSEG SMM range (ESMMTOP).
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2:1
7:4
Bit
Bit
7
6
5
4
3
0
Attr
RWL
RWL
RWL
RWL
Attr
RO
RV
RV
RV
16
0
62h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
63h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
00
0h
0
0
0
0
0
0
H_SMRAME: Enable High SMRAM
Controls the SMM memory space location (that is, above 1 MByte or below 1
MByte) When G_SMRAME is 1 and H_SMRAME is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses within the range FEDA_0000h to
FEDB FFFFh are remapped to DRAM addresses within the range 000A_0000h
to 000B_FFFFh. Once D_LCK has been set, this bit becomes read only.
MDAP: MDA Present
Since the MCH does not support MDA, this bit has no meaning.
Reserved
Reserved
G_SMRAME: Global SMRAM Enable
If set to a 1, then Compatible SMRAM functions are enabled, providing 128 KB
of DRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode). To enable Extended SMRAM function this bit has be set to 1. Refer to
the section on SMM for more details. Once D_LCK is set, this bit becomes read
only. (Moved from SMRAM bit3)
TSEG_SZ: TSEG Size
Selects the size of the TSEG memory block if enabled. Memory from
(ESMMTOP - TSEG_SZ) to ESMMTOP - 1 is partitioned away so that it may only
be accessed by the processor interface and only then when the SMM bit
(SMMEM#) is set in the request packet. Non-SMM accesses to this memory
region are sent to ESI when the TSEG memory block is enabled. Note that
once D_LCK is set, these bits become read only.
00: 512kB
01: 1MB
10: 2MB
11: 4MB
T_EN: TSEG Enable
Enabling of SMRAM memory for Extended SMRAM space only. When
G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the
appropriate physical address space. Note that once D_LCK is set, this bit
becomes read only.
Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description