NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 91

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.2.11
3.8.2.12
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
EXSMRAMC - Expansion System Management RAM Control Register
Other address mapping registers such as BCTRL (VGAEN), MBASE/LIMIT, PMBASE/
LIMIT, and so forth, are included with the PCI Express registers described in this
chapter.
HECBASE - PCI Express Extended Configuration Base Address Register
This register defines the base address of the enhanced PCI Express configuration
memory.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:24
3:0
6:0
Bit
Bit
Bit
7
RWC
Attr
RWL
Attr
Attr
RV
RV
16
0
63h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
60h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
64h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
Default
1h
0h
0h
0
ESMMTOP: Top of Extended SMM Space (TSEG)
This field contains the address that corresponds to address bits 31 to 28. This
field points to the top (+1) of extended SMM space below 4 GB. Addresses
below 4 GB (A[39:32] must be 0) that fall in this range are decoded to be in
the extended SMM space and should be routed according to
TSEG_SZ can be 512 KB, 1 MB, 2 MB, or 4 MB, depending on the value of
EXSMRC.TSEG_SZ.
ESMMTOP is relocatable to accommodate software that wishes to configure the
TSEG SMM space before MMIO space is known.
This field defaults to point to the same address as TOLM. Note that ESMMTOP
cannot be greater than TOLM otherwise the chipset will not function
deterministically.
Note that once D_LCK is set, this field becomes read only.
E_SMERR: Invalid SMRAM Access
This bit is set when CPU has accessed the defined memory ranges in High SMM
Memory and Extended SMRAM (T-segment) while not in SMM space and with
the D-OPEN bit = 0. The MCH will set this bit if any In-Bound access from I/O
device targeting SMM range that gets routed to the ESI port (master abort).
Refer to
does a cache line eviction (EWB or IWB) to SMM ranges regardless of
SMMEM# on FSB.
It is software's responsibility to clear this bit. The software must write a 1 to
this bit to clear it.
Reserved
Reserved
Section 4.4.3
ESMMTOP-TSEG_SZ <= Address < ESMMTOP
for details. The MCH will not set this bit when processor
Description
Description
Description
Section
4.3.3:
91