NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 99

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Register Description
3.8.5.4
3.8.5.5
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SPAD[3:0] - Scratch Pad Registers
These scratch pad registers each provide 32 read/writable bits that can be used by
software. They are also aliased to fixed memory addresses.
SPADS[3:0] - Sticky Scratch Pad
These sticky scratch pad registers each provide 32 read/writable bits that can be used
by software. They are also aliased to fixed memory addresses.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
10:0
Bit
11
31:0
31:0
Bit
Bit
RWST
Attr
RV
Attr
RW
RWST
Attr
16
0
44h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
DCh, D8h, D4h, D0h
Intel 5000P Chipset, Intel 5000V Chipset
16
0
ECh, E8h, E4h, E0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
00000000h
Default
Default
00000000h
Default
0h
1
Scratch Pad value. These bits have no effect on the hardware.
BUSPARK: Request Bus Parking Disable
If set, A[15]# is asserted and the processor may not park on the system
bus. Default is to disable busparking
Reserved
Scratch Pad value. These sticky bits have no effect on the hardware.
Description
Description
Description
99

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