PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet
PSD813F2-A-70J
Specifications of PSD813F2-A-70J
Related parts for PSD813F2-A-70J
PSD813F2-A-70J Summary of contents
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... May 2009 Flash in-system programmable (ISP) peripherals for 8-bit MCUs ■ Programmable power management ■ Packages are ECOPACK Table 1. Device summary Reference PSD8XXFX Doc ID 7833 Rev 7 PSD8XXFX PQFP52 (M) PLCC52 (J) TQFP64 (U) ® Part number PSD813F2 PSD813F4 PSD813F5 PSD833F2 PSD834F2 PSD853F2 PSD854F2 1/128 www.st.com 1 ...
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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PSD8XXFX 7.8 Toggle flag (DQ6 ...
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Contents 14.4 Output macrocell (OMC ...
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PSD8XXFX 16.17 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PSD8XXFX List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. CPLD combinatorial timing (3 V devices ...
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PSD8XXFX List of figures Figure 1. PQFP52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Flash memory IAP via the UART of the host MCU ● Memory paging to execute code across several PSD memory pages ● Loading, reading, and manipulation of PSD macrocells by the MCU. Table 2. Product range Primary Flash (1) memory Part number (8 sectors) PSD813F2 1 Mbit PSD813F4 1 Mbit PSD813F5 1 Mbit PSD833F2 1 Mbit PSD834F2 2 Mbit Secondary I/O ...
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Summary description Table 2. Product range (continued) Primary Flash (1) memory Part number (8 sectors) PSD853F2 1 Mbit PSD854F2 2 Mbit 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management ...
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PSD8XXFX Figure 2. PLCC52 connections PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 Doc ID 7833 Rev 7 Summary description AD15 ...
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Summary description Figure 3. TQFP64 connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 6 PC5 PC4 GND 10 GND 11 PC3 12 PC2 13 14 PC1 PC0 ...
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PSD8XXFX 2 Pin description Table 3. PLCC52 pin description Pin name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where ...
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Pin description Table 3. PLCC52 pin description Pin name Pin Type These pins make up port A. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or ...
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PSD8XXFX Table 3. PLCC52 pin description Pin name Pin Type PC3 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. ...
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Pin description Table 3. PLCC52 pin description Pin name Pin Type PD2 pin of port D. This port pin can be configured to have the following functions: MCU I/O - write to or read from a standard output or input ...
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PSD8XXFX Figure 4. PSD block diagram Doc ID 7833 Rev 7 Pin description AI02861f 19/128 ...
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PSD architectural overview 3 PSD architectural overview PSD devices contain several major functional blocks. PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. ...
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PSD8XXFX 3.4 I/O ports The PSD has 27 individually configurable I/O pins distributed over the four ports (Port and D). Each I/O pin can be individually configured for different functions. ports can be configured as standard MCU ...
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PSD architectural overview The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs ...
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PSD8XXFX 4 Development system The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description ...
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PSD register description and address offset 5 PSD register description and address offset Table 7 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is ...
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PSD8XXFX Table 8. Register address offset (continued) Register Port A Port B Port C Port D name Mask macrocells 22 AB Mask macrocells BC Primary Flash Protection Secondary Flash memory Protection JTAG Enable PMMR0 PMMR2 Page VM 1. Other registers ...
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Detailed operation 6 Detailed operation As shown in Figure ● Memory blocks ● PLD blocks ● MCU bus interface ● I/O ports ● Power management unit (PMU) ● JTAG interface The functions of each block are described in the following ...
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PSD8XXFX 6.2 Description of primary Flash memory and secondary Flash memory The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be ...
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Detailed operation (1)(2)(3) Table 10. Instructions FS0-FS7 or CSBOOT0- Instruction CSBOOT3 (4) “READ” (5) READ Read Main AAh@ 1 (6) Flash ID X555h Read Sector AAh@ (6)(7) Protection 1 X555h (8) Program a AAh@ 1 (8) ...
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PSD8XXFX 8. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the ...
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Instructions 7 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are ...
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... The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see operation, address bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be high. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h. 7.5 ...
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Instructions (1)(2)(3) Table 11. Status bits FS0- Functional FS7/CSBOOT0- block CSBOOT3 Flash memory Not guaranteed value, can be read either '1' or ’0.’ 2. DQ7-DQ0 represent the data bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 ...
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PSD8XXFX 7.9 Error flag (DQ5) During a normal program or erase cycle, the Error flag bit (DQ5 ’0.’ This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk ...
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Programming Flash memory 8 Programming Flash memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may erase ...
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PSD8XXFX Figure 6. Data Polling flowchart 8.2 Data Toggle Checking the Toggle flag bit (DQ6 method of determining whether a program or erase cycle is in progress or has completed. When the MCU issues a Program instruction, the ...
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Programming Flash memory any location within the sector being erased to get the Toggle flag bit (DQ6) and the Error flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. 8.3 Unlock Bypass (PSD833F2x, ...
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PSD8XXFX Figure 7. Data Toggle flowchart START READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 DQ6 NO = TOGGLE YES FAIL PASS AI01370B Doc ID 7833 Rev 7 Programming Flash memory 37/128 ...
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Erasing Flash memory 9 Erasing Flash memory 9.1 Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in wrong, the Bulk Erase instruction aborts and the ...
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PSD8XXFX A Suspend Sector Erase instruction executed during an Erase timeout period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle flag bit (DQ6) stops toggling when the PSD internal logic is suspended. The status ...
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... An Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1') during a Flash memory program or erase cycle. On the PSD813F2/3/4/5, the Reset Flash instruction puts the Flash memory back into normal READ mode. It may take the Flash memory few milliseconds to complete the Reset cycle ...
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PSD8XXFX 10.3 Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a program or erase ...
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SRAM 11 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express Configuration. 42/128 ...
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PSD8XXFX 12 Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these ...
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Sector Select and SRAM Select PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 14 Figure 8. Priority level of memory and I/O components 12.3 Configuration modes for MCUs with separate program ...
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PSD8XXFX Figure 10. 8031 memory modules – combined space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 Table 14. VM register Bit 7 Bit 6 ...
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Page register 13 Page register The 8-bit Page register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page ...
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PSD8XXFX 14 PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD contains ...
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PLDS Table 15. DPLD and CPLD inputs (continued) Input source Page register Macrocell AB feedback Macrocell BC feedback Secondary Flash memory Program Status Bit 1. The address inputs are A19-A4 in 80C51XA mode. 48/128 Input name PGR7-PGR0 MCELLAB.FB7-FB0 MCELLBC.FB7-FB0 Ready/Busy ...
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PSD8XXFX Figure 12. PLD diagram PORTS I/O BUS INPUT PLD Doc ID 7833 Rev 7 PLDS 49/128 ...
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PLDS 14.2 Decode PLD (DPLD) The DPLD, shown in components. The DPLD can be used to generate the following decode signals: ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) ● 4 Sector Select ...
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PSD8XXFX 14.3 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three ...
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PLDS Figure 14. Macrocell and I/O port BUS INPUT PLD 52/128 MUX MUX ARRAY AND BUS INPUT PLD Doc ID 7833 Rev 7 PSD8XXFX MUX MUX ...
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PSD8XXFX 14.4 Output macrocell (OMC) Eight of the Output macrocells (OMC) are connected to ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to ports B and C pins and are named as ...
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PLDS 14.5 Product Term Allocator The CPLD has a Product Term Allocator. The PSDabel compiler uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated: ...
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PSD8XXFX If the Output macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be ...
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PLDS 14.9 Input macrocells (IMC) The CPLD has 24 input macrocells (IMC), one for each pin on ports A, B, and C. The architecture of the input macrocells (IMC) is shown in are individually configurable, and can be used as ...
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PSD8XXFX Figure 16. Input macrocell ARRAY AND BUS INPUT PLD Doc ID 7833 Rev 7 PLDS 57/128 ...
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PLDS Figure 17. Handshaking communication using input macrocells 58/128 Doc ID 7833 Rev 7 PSD8XXFX ...
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PSD8XXFX 15 MCU bus interface The “no-glue logic” MCU bus interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are shown in Table 17. The ...
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MCU bus interface 15.1 PSD interface to a multiplexed 8-bit bus Figure 18 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to ...
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PSD8XXFX 15.4 MCU bus interface examples Figure 20, Figure connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified ...
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MCU bus interface 15.5 80C31 Figure 20 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Select Enable (PSEN, CNTL2), ...
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PSD8XXFX 15.6 80C251 The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown in Figure as ...
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MCU bus interface Figure 22. Interfacing the PSD with the 80C251, with RD and PSEN inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 ...
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PSD8XXFX 15.7 80C51XA The Philips 80C51XA MCU family supports 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, ...
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MCU bus interface 15.8 68HC11 Figure 24 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ and WR signals ...
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PSD8XXFX 16 I/O ports There are four programmable I/O ports: ports and D. Each of the ports is eight bits except port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple ...
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I/O ports 16.2 Port operating modes The I/O ports have several modes of operation. Some modes can be defined using PSDabel, some by the MCU writing to the Control registers in CSIOP space, and some by both. The modes that ...
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PSD8XXFX 16.3 MCU I/O mode In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address ...
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I/O ports Table 20. Port operating modes (continued) Port mode Address Out Address In Data port Peripheral I/O JTAG ISP 1. Can be multiplexed with other I/O functions. Table 21. Port operating mode settings Defined in Mode PSDabel MCU I/O ...
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PSD8XXFX 16.6 Address In mode For MCUs that have more than 16 address signals, the higher addresses can be connected to port and D. The address input can be latched in the input macrocell (IMC) by Address ...
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I/O ports 16.10 Port configuration registers (PCR) Each port has a set of port configuration registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given ...
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PSD8XXFX Table 23. Port configuration registers (PCR)t Register name Control Direction (1) Drive Select 1. See Table 27 for Drive register bit definition. Table 24. Port Pin Direction Control, Output Enable P.T. not defined Direction register bit Table 25. Port ...
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I/O ports 16.14 Port Data registers The port Data registers, shown in data from the ports. and MCU access for each register type. The registers are described below. 16.15 Data In Port pins are connected directly to the Data In ...
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PSD8XXFX 16.19 Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port indicates the driver is in output mode indicates the driver is in ...
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I/O ports 16.21 Port C – functionality and structure Port C can be configured to perform one or more of the following functions (see ● MCU I/O mode ● CPLD Output – McellBC7-McellBC0 outputs can be connected to port B ...
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PSD8XXFX Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: ● Address Strobe (ALE/AS, PD0) ● CLKIN (PD1) as input to the macrocells flip-flops and APD counter ● PSD Chip Select input (CSI, ...
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I/O ports Figure 30. Port D external Chip Select signals 78/128 ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT Doc ID 7833 Rev 7 PSD8XXFX DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 ...
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PSD8XXFX 17 Power management All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ● All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with ...
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Power management 17.1 Automatic Power-down (APD) Unit and Power-down mode The APD Unit, shown in activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE/AS, PD0) stops, a four bit ...
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PSD8XXFX Figure 31. APD unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE RESET EDGE CSI DETECT CLKIN DISABLE FLASH/EEPROM/SRAM Table 30. PSD timing and standby current during Power-down mode Mode PLD propagation delay (1) Power-down Normal ...
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Power management Figure 32. Enable Power-down flowchart 17.4 PLD power management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo mode is off and ...
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PSD8XXFX Table 31. Power Management mode registers PMMR0 Bit Name 0 = CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN on (PD1) Powers-up the PLD when Turbo Bit is ’0.’ Bit 4 PLD Array ...
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Power management 17.5 PSD Chip Select input (CSI, PD2) PD2 of port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O ...
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PSD8XXFX 18 Reset timing and device status at reset 18.1 Power-up reset Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t steady. During this period, the device loads internal configurations, clears some of the registers and sets ...
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Reset timing and device status at reset Figure 33. Reset (RESET) timing V (min NLNH-PO Power-On Reset RESET Table 34. Status during Power-on reset, Warm reset and Power-down mode Port configuration MCU I/O Input mode Valid ...
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PSD8XXFX 19 Programming in-circuit using the JTAG serial interface The JTAG Serial Interface block can be enabled on port C (see (primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may be programmed through the JTAG Serial ...
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Programming in-circuit using the JTAG serial interface Reset (RESET) will prevent or interrupt JTAG operations if the JTAG enable register is used to enable the JTAG pins. The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PSDsoft ...
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PSD8XXFX Table 35. JTAG port signals Port C pin PC0 PC1 PC3 PC4 PC5 PC6 Programming in-circuit using the JTAG serial interface JTAG signals TMS TCK TSTAT TERR TDI TDO Doc ID 7833 Rev 7 Description mode Select Clock Status ...
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Initial delivery state 20 Initial delivery state When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration register bits are set to ’0.’ The code, configuration, and PLD logic ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 37. ...
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AC/DC parameters 22 AC/DC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device: ● DC electrical specifications ● AC timing specifications – PLD timings Combinatorial timings Synchronous clock mode Asynchronous clock ...
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PSD8XXFX Figure 34. PLD I 110 100 Figure 35. PLD Table 38. Example of PSD typical power calculation at V ...
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AC/DC parameters Table 38. Example of PSD typical power calculation at V Number of product terms used (from fitter report total product terms Turbo mode I total CC 1. This is the operating power with no EEPROM WRITE ...
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PSD8XXFX Table 39. Example of PSD typical power calculation at V (from fitter report total product terms Turbo mode I total CC 1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in ...
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AC/DC parameters Table 42. AC signal letters for PLD timing Letter Example time from address valid to ALE invalid. AVLX Table 43. ...
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PSD8XXFX Table 45. Capacitance Symbol Input capacitance (for input C IN pins) Output capacitance (for C OUT input/output pins) Capacitance (for C VPP CNTL2/V 1. Sampled only, not 100% tested. 2. Typical values are for T Figure 36. AC measurement ...
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AC/DC parameters Table 46. DC characteristics (5 V devices) Symbol Parameter V Input high voltage IH V Input low voltage IL V Reset high level input voltage IH1 V Reset low level input voltage IL1 V Reset pin hysteresis HYS ...
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PSD8XXFX Table 47. DC Characteristics (3 V devices) Symbol Parameter V High level input voltage IH V Low level input voltage IL V Reset high level input voltage IH1 V Reset low level input voltage IL1 V Reset pin hysteresis ...
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AC/DC parameters Figure 39. Input to output disable / enable INPUT TO ENABLE/DISABLE Table 48. CPLD combinatorial timing (5 V devices) Symbol Parameter CPLD input pin/feedback CPLD combinatorial output CPLD input to CPLD t EA output enable ...
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PSD8XXFX Table 49. CPLD combinatorial timing (3 V devices) (continued) Symbol Parameter CPLD register clear t ARPW or preset pulse width t CPLD array delay ARD 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by ...
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AC/DC parameters Table 50. CPLD macrocell Synchronous clock mode timing (5 V devices) (continued) Symbol Parameter Conditions CPLD array t Any macrocell ARD delay Minimum clock t t (2) MIN period 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, ...
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PSD8XXFX Figure 41. Asynchronous Reset / Preset RESET/PRESET REGISTER OUTPUT Figure 42. Asynchronous Clock mode Timing (product term clock) REGISTERED OUTPUT Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) Symbol Parameter Conditions Maximum frequency 1/(t SA External ...
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AC/DC parameters Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) (continued) Symbol Parameter Conditions Clock to t COA output delay CPLD array t Any macrocell ARDA delay Minimum t 1/f MINA clock period Table 53. CPLD macrocell ...
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PSD8XXFX Figure 43. Input macrocell timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 54. Input macrocell timing (5 V devices) Symbol Parameter t Input setup time IS t Input hold time IH t NIB input high time INH ...
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AC/DC parameters Figure 44. READ timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV 1. t and t are not required for 80C251 in Page mode ...
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PSD8XXFX Table 56. READ timing (5 V devices) (continued) Symbol Parameter t R/W setup time to Enable THEH t R/W hold time After Enable ELTL Address input valid to t AVPV Address output delay 1. Any input used to select ...
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AC/DC parameters Figure 45. WRITE timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS Table 58. WRITE timing (5 V devices) Symbol Parameter t ALE or AS pulse ...
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PSD8XXFX Table 58. WRITE timing (5 V devices) (continued) Symbol Parameter Trailing edge port output t WHPV valid using I/O port data register Data valid to port output valid t using macrocell register DVMV Preset/Clear Address input ...
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AC/DC parameters Table 59. WRITE timing (3 V devices) (continued) Symbol Parameter t Address input valid to address output delay AVPV WR valid to port output valid using t WLMV macrocell register Preset/Clear 1. Any input used to select an ...
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PSD8XXFX 1. The whole memory is programmed to 00h before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Figure 46. Peripheral I/O READ timing ALE/ BUS ...
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AC/DC parameters Table 63. Port A Peripheral Data mode READ timing (3V devices) Symbol Parameter t Address valid to data valid AVQV–PA t CSI valid to data valid SLQV– data valid t RLQV– data valid 8031 ...
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PSD8XXFX Table 65. Port A Peripheral Data mode WRITE timing (3 V devices) Symbol Parameter data propagation delay WLQV–PA t Data to port A data propagation delay DVQV– invalid to port A tri-state WHQZ–PA 1. ...
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AC/DC parameters Figure 49. ISC timing t TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 68. ISC timing (5 V devices) Symbol Parameter Clock (TCK, PC1) frequency (except for t ISCCF PLD) Clock (TCK, PC1) high time (except for t ISCCH ...
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PSD8XXFX Table 69. ISC timing (3 V devices) Symbol Parameter Clock (TCK, PC1) frequency (except for t ISCCF PLD) Clock (TCK, PC1) high time (except for t ISCCH PLD) Clock (TCK, PC1) low time (except for t ISCCL PLD) t ...
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Package mechanical 23 Package mechanical In order to meet environmental requirements, ST offers this device in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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PSD8XXFX Figure 50. PQFP52 - 52-pin plastic quad flat package mechanical drawing 1. Drawing is not to scale. Table 72. PQFP52 - 52-pin plastic quad flat package mechanical dimensions Symbol ...
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Package mechanical Figure 51. PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing M 1. Drawing is not to scale. Table 73. PLCC52-52-lead plastic lead chip carrier mechanical dimensions Symbol ...
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PSD8XXFX Figure 52. TQFP64 - 64-lead thin quad flatpack, package outline 1. Drawing is not to scale. Table 74. TQFP64 - 64-lead thin quad flatpack, package mechanical data Symb ...
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Part numbering 24 Part numbering Table 75. Ordering information scheme Example: Device Type PSD8 = 8-bit PSD with register Logic SRAM Capacity Kbit Kbit 5 = 256 Kbit Flash Memory Capacity ...
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PSD8XXFX Appendix A PQFP52 pin assignments Table 76. PQFP52 connections (see Features) Pin number ...
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PQFP52 pin assignments Table 76. PQFP52 connections (see Features) (continued) 122/128 Pin number Doc ID 7833 Rev 7 PSD8XXFX Pin ...
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PSD8XXFX Appendix B PLCC52 pin assignments Table 77. PLCC52 connections (see Features) Pin number ...
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PLCC52 pin assignments Table 77. PLCC52 connections (see Features) (continued) 124/128 Pin number Doc ID 7833 Rev 7 PSD8XXFX Pin ...
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PSD8XXFX Appendix C TQFP64 pin assignments Table 78. TQFP64 connections (see Features) Pin number ...
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TQFP64 pin assignments Table 78. TQFP64 connections (see Features) (continued) 126/128 Pin number ...
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PSD8XXFX Revision history Table 79. Document revision history Date 15-Oct-99 27-Oct-00 30-Nov-00 23-Oct-01 07-Apr-03 12-Jun-03 02-Oct-03 17-Nov-03 04-Jun-04 05-Jan-06 13-Feb-2009 05-May-2009 Revision 1.0 Initial release as a WSI document 1.1 Port A Peripheral Data mode Read Timing, changed to 50 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...