ISP1160BM,518 NXP Semiconductors, ISP1160BM,518 Datasheet

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ISP1160BM,518

Manufacturer Part Number
ISP1160BM,518
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1160BM,518

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Package Type
PQFP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
1. General description
2. Features
The ISP1160/01 is an embedded Universal Serial Bus (USB) Host Controller (HC) that
complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at
full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1160/01 provides two
downstream ports. Each downstream port has an overcurrent (OC) detection input pin
and power supply switching control output pin. The downstream ports for the HC can be
connected with any USB compliant USB devices and USB hubs that have USB upstream
ports.
The ISP1160/01 is well suited for embedded systems and portable devices that require a
USB host. The ISP1160/01 brings high flexibility to the systems that have it built-in. For
example, a system that has the ISP1160/01 built-in allows it to be connected to a device
that has a USB upstream port, such as a USB printer, USB camera, USB keyboard, USB
mouse, among others.
Embedded USB host controller
Rev. 07 — 29 September 2009
Complies with Universal Serial Bus Specification Rev. 2.0
Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Adapted from Open Host Controller Interface Specification for USB Release 1.0a
Selectable one or two downstream ports for HC
High-speed parallel interface to most of the generic microprocessors and Reduced
Instruction Set Computer (RISC) processors such as:
Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC
Supports single-cycle and burst mode DMA operations
Built-in FIFO buffer RAM for the HC (4 kbytes)
Endpoints with double buffering to increase throughput and ease real-time data
transfer for isochronous (ISO) transactions
6 MHz crystal oscillator with integrated PLL for low EMI
Built-in software selectable internal 15 kΩ pull-down resistors for HC downstream
ports
Dedicated pins for suspend sensing output and wake-up control input for flexible
applications
Operation at either +5 V or +3.3 V power supply voltage
Operating temperature range from −40 °C to +85 °C
Available in two LQFP64 packages (SOT314-2 and SOT414-1).
Hitachi SuperH SH-3 and SH-4
MIPS-based RISC
ARM7, ARM9, and StrongARM
Product data sheet

Related parts for ISP1160BM,518

ISP1160BM,518 Summary of contents

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Embedded USB host controller Rev. 07 — 29 September 2009 1. General description The ISP1160/ embedded Universal Serial Bus (USB) Host Controller (HC) that complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 ...

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Applications Personal Digital Assistant (PDA) Digital camera Third-generation (3-G) phone Set-Top Box (STB) Information Appliance (IA) Photo printer MP3 jukebox Game console. 4. Ordering information Table 1. Ordering information Commercial Package description product code LQFP64; 64 leads; body 10 ...

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H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 22 RD_N 21 CS_N 23 MICROPROCESSOR WR_N 59 ...

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Pinning information 6.1 Pinning DGND DGND D10 11 D11 12 D12 13 D13 14 DGND 15 D14 16 (1) ISP1160/01 is the marking on the IC for the ISP1160BD01TM. (2) ...

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Table 2. [1] Symbol DGND D8 D9 D10 D11 D12 D13 DGND D14 D15 DGND V HOLD1 n.c. CS_N RD_N WR_N V HOLD2 DREQ n.c. DACK_N ISP1160-01_7 Product data sheet Pin description LQFP64 …continued Pin Type ...

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Table 2. [1] Symbol TEST_HIGH INT n.c. n.c. RESET_N NDP_SEL EOT DGND n.c. TEST_LOW n.c. TEST_LOW H_WAKEUP n.c. H_SUSPEND XTAL1 XTAL2 DGND H_PSW1_N H_PSW2_N n.c. n.c. H_DM1 ISP1160-01_7 Product data sheet Pin description LQFP64 …continued Pin Type Description 28 - ...

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Table 2. [1] Symbol H_DP1 H_DM2 H_DP2 H_OC1_N H_OC2_N V CC AGND V REG(3V3) A0 LOW_PW n.c. DGND D0 D1 [1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. ISP1160-01_7 Product data sheet Pin description ...

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Functional description 7.1 PLL clock multiplier A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are ...

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Fig 3. Programmed I/O interface between a microprocessor and the ISP1160/01. 8.2 DMA mode The ISP1160/01 also provides the DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by the DMA operation between ...

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Control registers access by PIO mode 8.3.1 I/O port addressing Table 3 shows the ISP1160/01’s I/O port addressing. Complete decoding of the I/O port address should include the chip select signal CS_N and the address line A0. However, the ...

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Fig 6. 16-bit register access cycle. Most of the ISP1160/01’s internal control registers are 16-bit wide. Some of the internal control registers, however, are 32-bit wide. internal control register is accessed. The complete cycle of accessing a 32-bit register consists ...

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Fig 9. Internal FIFO buffer RAM access cycle. Figure 9 shows a complete access cycle of the HC internal FIFO buffer RAM. For a write cycle, the microprocessor first writes the FIFO buffer RAM’s command code ...

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DACK_N RD_N or WR_N 1/2 byte count of transfer data. Fig 10. DMA transfer in single-cycle mode. DREQ DACK_N RD_N or WR_N D [ 15:0 ] data #1 data #K EOT N = 1/2 ...

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Figure 12 through the HcHardware Configuration register (see disable or enable the signals. Fig 12. Interrupt pin operating modes. 8.6.2 Interrupt output pin (INT) To program the four configuration modes of the HC’s interrupt output signal (INT), set InterruptPinTrigger and ...

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HcInterruptEnable register MIE RHSC FNO group 2 RHSC FNO HcInterruptStatus register Fig 13. HC interrupt logic. There are two groups of interrupts represented by group 1 and group 2 in pair of ...

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To re-enable the interrupt generation: 1. Set all bits in the HcμPInterrupt register. 2. Set the InterruptPinEnable bit to logic 1. Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register latches the interrupt output. When this bit is set to logic ...

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The USB states are reflected in the HostControllerFunctionalState field of the HcControl register (01H to read, 81H to write), which is located at bits 7 and 6 of the register. The HCD can perform only the USB state transitions shown ...

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Entry: The normal entry point. The microprocessor returns to this point when there are HC requests. 4. Need USB traffic: USB devices need the HC to generate USB traffic when they have USB traffic requests such as: a. Connecting ...

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Fig 16. PTD data in FIFO buffer RAM. The PTD data structure is used by the HC to define a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is ...

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Table 5. Proprietary Transfer Descriptor (PTD): bit description Symbol Access ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD. CompletionCode[3:0] R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Active ...

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Table 5. Proprietary Transfer Descriptor (PTD): bit description Symbol Access DirectionPID[1: B5_5 R/W This bit is logic 0 at power-on reset. When this feature is not used, software used for the ISP1160/01 is the same ...

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ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO buffer RAM for only ATL transfers. Fig 17. HC internal FIFO buffer RAM partitions. The actual requirement for the buffer RAM needs to ...

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Data organization PTD data is used for every data transfer between a microprocessor and the USB bus, and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the payload data is placed just after ...

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Fig 19. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation and C program example Figure 20 mode. The ISP1160/01 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port ...

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Host bus I 000H 001H 3FFH ITL0 buffer RAM (8-bit width) Fig 20. PIO access to internal FIFO buffer RAM. Following is an example program that shows how to write data into the ATL ...

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ATL buffer RAM #include <conio.h> #include <stdio.h> #include <dos.h> //Define register commands #define wHcTransferCounter 0x22 #define wHcuPInterrupt 0x24 #define wHcATLBufferLength 0x2b #define wHcBufferStatus 0x2c // Define I/O Port Address for HC #define HcDataPort 0x290 #define ...

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HcRegWrite(wHcuPInterrupt,0x04); //Clear EOT interrupt bit //HcRegWrite(wHcITLBufferLength,0x0); HcRegWrite(wHcATLBufferLength,0x1000); //RAM full use for ATL //Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50); wCount = 0x28; //Get word count outport (HcCmdPort,0x00c1); //Command for ATL buffer write //write 80 (0x50) bytes of data ...

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Table 6. Run results of the C program example Observed items HC not initialized and not in USBOperational state HcBufferStatus register Bit 2 (ATLBufferFull) Bit 5 (ATLBufferDone) USB traffic on USB Bus 9.5 HC operational model Upon power up, the ...

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For example, the HCD writes ISO_A data into the ITL0 buffer in the first frame. This will cause the HcBufferStatus register to show that the ITL0 buffer is full by setting bit ITL0BufferFull to logic 1. At this stage, the ...

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N) Fig 22. HC time domain behavior: example 2. In example 3 of the next frame has occurred. This will result in undefined behavior for the ISO data on the USB bus in frame (depending on ...

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Using either internal or external 15 kΩ resistors. Fig 24. Use of 15 kΩ pull-down resistors on downstream ports. 9.8 Overcurrent detection and power switching control A downstream port provides 5 V power supply to V hardware functions to monitor ...

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Using an internal OC detection circuit The internal OC detection circuit can be used only when power supply. The HCD must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, to logic 1. An application using the ...

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Using an external OC detection circuit When detection circuit cannot be used. An external OC detection circuit must be used instead. Regardless of the V used. To use an external OC detection circuit, AnalogOCEnable, bit 10 ...

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XOSC_6MHz XOSC On On VOLTAGE REGULATOR Fig 28. ISP1160/01 suspend and resume clock scheme. In the suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal ...

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Wake-up by pin CS_N (software wake-up) During the USBSuspend state, an external microprocessor issues a chip select signal through pin CS_N to the ISP1160/01. This method of access to the ISP1160/01 internal registers is a software wake-up. 9.9.2.3 Wake-up ...

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Table 7. HC registers summary Address (Hex) Register Read Write 0D 8D HcFmInterval 0E N/A HcFmRemaining 0F N/A HcFmNumber 11 91 HcLSThreshold 12 92 HcRhDescriptorA 13 93 HcRhDescriptorB 14 94 HcRhStatus 15 95 HcRhPortStatus[ HcRhPortStatus[ HcHardwareConfiguration ...

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Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol Reset 0 0 Access R R Table 9. Bit 10.1.2 HcControl register (R/W: 01H/81H) The HcControl register defines the operating ...

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Table 11. Bit 10.1.3 HcCommandStatus register (R/W: 02H/82H) The HcCommandStatus register is used by the HC to receive commands issued by the HCD, and it also reflects the ...

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Table 12. HcCommandStatus register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R R Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol ...

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Table 14. HcInteruptStatus register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol ...

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A bit is set in the HcInterruptStatus register • The corresponding bit in the HcInterruptEnable register is set • Bit MasterInterruptEnable is set. Writing a logic bit in this register sets the corresponding bit, whereas writing ...

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Table 17. Bit 10.1.6 HcInterruptDisable register (R/W: 05H/85H) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a ...

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Table 19. Bit 10.2 HC frame counter registers 10.2.1 HcFmInterval register (R/W: 0DH/8DH) The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive ...

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Table 21. Bit 10.2.2 HcFmRemaining register (R: 0EH) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Code (Hex): 0E — read ...

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Table 23. Bit 10.2.3 HcFmNumber register (R: 0FH) The HcFmNumber register is a 16-bit counter. It provides a timing reference for events happening in the HC and the HCD. The HCD may use ...

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HcLSThreshold register (R/W: 11H/91H) The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the HC nor the HCD is ...

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Four 32-bit registers have been defined: • HcRhDescriptorA • HcRhDescriptorB • HcRhStatus • HcRhPortStatus[1:NDP] Each register is read and written as a DWORD. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB ...

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Table 29. Bit 10.3.2 HcRhDescriptorB register (R/W: 13H/93H) The HcRhDescriptorB register is the second register of two describing the characteristics of the Root ...

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Table 30. HcRhDescriptorB register: bit allocation Bit 31 30 Symbol Reset N/A N/A Access R R Bit 23 22 Symbol Reset N/A N/A Access R R Bit 15 14 Symbol Reset N/A N/A Access R R Bit 7 6 Symbol ...

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Table 32. HcRhStatus register: bit allocation Bit 31 30 Symbol CRWE Reset 0 0 Access W R Bit 23 22 Symbol Reset 0 0 Access R R Bit 15 14 Symbol DRWE Reset 0 0 Access R/W R Bit 7 ...

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Table 33. Bit 10.3.4 HcRhPortStatus[1:2] (R/W [1]:15H/95H, [2]: 16H/96H) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number ...

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Table 34. HcRhPortStatus[1:2] register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol reserved Reset 0 0 Access R/W R/W Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 ...

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Table 35. Bit ISP1160-01_7 Product data sheet HcRshPortStatus[1:2] register: bit description Symbol Description CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD writes a logic ...

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Table 35. Bit 4 3 ISP1160-01_7 Product data sheet HcRshPortStatus[1:2] register: bit description Symbol Description PRS On read—PortResetStatus: When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is ...

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Table 35. Bit 10.4 HC DMA and interrupt control registers 10.4.1 HcHardwareConfiguration register (R/W: 20H/A0H) Code (Hex): 20 — read Code (Hex): A0 — write ISP1160-01_7 Product data sheet HcRshPortStatus[1:2] register: bit description Symbol Description PSS On ...

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Table 36. HcHardwareConfiguration register: bit allocation Bit 15 14 Symbol reserved Reset 0 0 Access R/W R/W Bit 7 6 Symbol EOTInput DACKInput Polarity Polarity Reset 0 0 Access R/W R/W Table 37. Bit Symbol ...

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HcDMAConfiguration register (R/W: 21H/A1H) Code (Hex): 21 — read Code (Hex): A1 — write Table 38. HcDMAConfiguration register: bit allocation Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol reserved BurstLen[1:0] Reset 0 0 ...

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HC will generate an internal EOT signal to set bit 2 (AllEOTInterrupt) of the HcμPInterrupt register, and also update the HcBufferStatus register. Code (Hex): 22 — read Code (Hex): A2 — write Table 40. HcTransferCounter ...

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Table 43. Bit 10.4.5 HcμPInterruptEnable register (R/W: 25H/A5H) The bits 6:0 in this register are the same as those in the HcμPInterrupt register. They are used together with bit 0 ...

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Table 44. HcμPInterruptEnable register: bit allocation Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol reserved ClkReady Reset 0 0 Access R/W R/W Table 45. Bit ...

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Table 46. HcChipID register: bit allocation Bit 15 14 Symbol Reset 0 1 Access R R Bit 7 6 Symbol Reset 0 0 Access R R Table 47. Bit 10.5.2 HcScratch register (R/W: 28H/A8H) This register is ...

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Bit 7 6 Symbol Reset 0 0 Access W W Table 51. Bit 10.6 HC buffer RAM control registers 10.6.1 HcITLBufferLength register (R/W: 2AH/AAH) Write to this register to assign the ITL buffer size in bytes: ITL0 ...

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Remark: The maximum total RAM size is 1000H (4096 in decimal) bytes. That means ITL0 (length) + ITL1 (length) + ATL (length) ≤ 1000H bytes. For example, if ATL buffer length has been set to be 800H, then the maximum ...

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Table 57. Bit 10.6.4 HcReadBackITL0Length register (R: 2DH) This register’s value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter ...

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Bit 7 6 Symbol Reset 0 0 Access R R Table 61. Bit Symbol RdITL1BufferLength[15:0] 10.6.6 HcITLBufferPort register (R/W: 40H/C0H) This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes ...

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Code (Hex): 41 — read Code (Hex): C1 — write Table 64. HcATLBufferPort register: bit allocation Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 65. Bit Symbol ...

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Power supply The ISP1160/01 can operate at either 3.3 V. When using the ISP1160/01’s power supply input, only V connected to the 5 V power supply. An application with power ...

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Power-on reset (POR) When typically (600 ns to 1000 ns when rising with respect supply circuit. To give a better view of the functionality, with dips at t2-t3 ...

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Limiting values Table 66. Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage to pin V CC(5V0) V supply voltage to pin V CC(3V3) V input voltage I latch-up current ...

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Static characteristics Table 68. Static characteristics; supply pins specified. Symbol Parameter internal regulator output REG(3V3) I operating supply ...

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Table 70. Static characteristics: analog I/O pins D+ and D− Symbol Parameter Input levels V differential input sensitivity DI V differential common mode voltage includes ...

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Dynamic characteristics Table 71. Dynamic characteristics Symbol Parameter Reset t pulse width on input RESET_N crystal oscillator running W(RESET_N) Crystal oscillator f crystal frequency ...

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Programmed I/O timing Table 73. Dynamic characteristics: programmed interface timing Symbol Parameter address set-up time before t AS WR_N HIGH t address hold time after WR_N HIGH AH Read timing t first RD_N/WR_N after A0 HIGH SHSL t CS_N ...

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CS_N A0 RD_N WR_N data D [ 15:0 ] valid Fig 35. Programmed interface timing. 17.2 DMA timing 17.2.1 Single-cycle DMA timing Table 74. Dynamic characteristics: single-cycle DMA timing Symbol Parameter Read/write timing t ...

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DREQ DACK_N D [ 15:0 ] (read 15:0 ] (write) RD_N or WR_N Fig 36. Single-cycle DMA timing. 17.2.2 Burst mode DMA timing Table 75. Dynamic characteristics: burst mode DMA timing Symbol Parameter Read/write timing (for 4-cycle and ...

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DREQ t RHSH t SLAL DACK_N RD_N or WR_N Fig 37. Burst mode DMA timing. 17.2.3 External EOT timing for single-cycle DMASETUP DACK_N Fig 38. External EOT timing for single-cycle DMA. 17.2.4 External EOT timing for burst mode DMA DACK_N ...

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Application information 18.1 Typical interface circuit + 3.3 V SH7709 + 3 15 CS5 RD_N RD/WR_N DREQ0 DACK0_N + 5 V CLKOUT EXTAL IRQ2 XTAL PTC0 PTC1 EXTAL2 ...

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There is a DMA channel standard control line: DREQ and DACK_N. The DREQ signal has programmable active levels. • An interrupt line INT is used by the HC. It has programmable level/edge and polarity (active HIGH or LOW). • ...

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MECHANISM CONTROL TASK IMAGE PROCESSING TASKS FILE MANAGEMENT PRINTER UI/CONTROL OS DEVICE DRIVERS MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER HOST STACK RISC ROM ISP1160/01 RAM LEN CONTROL Fig 41. The ISP1160/01 software model for DSC application. 19. Test information ...

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Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A ...

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LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT A ...

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Revision history Table 76. Revision history Document ID Release date ISP1160-01_7 20090929 • Modifications: Rebranded to the ST-Ericsson template. • Table 1 “Ordering • Removed soldering information. ISP1160-01_6 20090128 ISP1160-05 20041224 (9397 750 13963) ISP1160-04 20030704 (9397 750 11371) ...

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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description LQFP64 . . . . . . . . ...

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Figures Fig 1. Block diagram Fig 2. Pin configuration LQFP64.. . ...

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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...

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Package outline . . . . . . . . . . . . . . . . . . . . . . . . 80 21 Revision history . . . . . . . . . ...

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The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to ...

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