ICE3PCS01G Infineon Technologies, ICE3PCS01G Datasheet - Page 11

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ICE3PCS01G

Manufacturer Part Number
ICE3PCS01G
Description
Power Factor Correction ICs STANDALONE PFC CTRLR IN CCM
Manufacturer
Infineon Technologies
Datasheet

Specifications of ICE3PCS01G

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Figure 4
3.4.2
The switching frequency can be synchronized to the
external pulse signal after 6 external pulses delay once
the voltage at the FREQ pin is higher than 2.5V. The
synchronization means two points. Firstly, the PFC
switching frequency is tracking the external pulse
signal frequency. Secondly, the falling edge of the PFC
signal is triggered by the rising edge of the external
pulse signal. Figure 5 shows the blocks of frequency
setting and synchronization. The external R
combined with R
ensure pin voltage to be kept between 1.0V (clamped
externally) and 5V (maximum pin voltage). If the
external pulse signal has disappeared longer than
108µs (typical) the switching frequency will be
synchronized to internal clock set by the external
resistor R
Figure 5
Version 2.0
R
R
D
FREQ
SYN
SYN
Syn. clock
260
240
220
200
180
160
140
120
100
80
60
40
20
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250
FREQ
FREQ
External Synchronization
Frequency Versus R
.
Frequency Setting and
Synchronization
FREQ
Resistance
Frequency vs Resistance
1.0V
/kohm
Resistance/kohm
100
15
17
20
30
40
50
60
70
80
90
and the external diode D
Frequency
/kHz
278
249
211
141
106
86
74
62
55
49
43
OTA7
2.5V/1.25V
Resistance
/kohm
110
120
130
140
150
169
191
200
210
221
232
FREQ
Frequency
31.5
29.5
26.2
21.2
20.2
19.2
/kHz
40
36
34
25
23
C9
SYN
SYN
I
OSC
can
SYN
11
3.5
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
sensing voltage at VSENSE which is a resistive divider
tapping from V
sigma-delta ADC which has an internal reference of
2.5V and sampling rate of 3.55kHz (typical). The
voltage loop compensation is integrated digitally for
better dynamic response and saving design effort.
Figure 6 shows the important blocks of this voltage
loop.
Figure 6
3.5.1
In the PFC converter, an averaged current through the
output diode of rectified sine waveform charges the
output capacitor and results in a ripple voltage at the
output capacitor with a frequency two times of the line
frequency. In this digital PFC, a notch filter is used to
remove the ripple of the sensed output voltage while
keeping the rest of the signal almost uninfluenced. In
this way, an accurate and fast output voltage regulation
without influence of the output voltage ripple is
achieved.
3.5.2
The Proportion-Integration (PI) compensation of the
voltage loop is integrated digitally inside the IC. The
digital data out of the PI compensator is converted to
analog voltage for current loop control.
Input Voltage
Rectified
Av(I
V
IN
IN
)
PWM Generation
Current Loop
L
Boost
Voltage Loop
OUT
Notch Filter
Voltage Loop Compensation
+
. This loop is closed by the feedback
Voltage Loop
t
Nonlinear
Gain
OUT
OLP
OVP
. The pin VSENSE is the input of
Q
B
R
Functional Description
PI Filter
GATE
500 ns
Q
Q
OVP
R
S
Notch
Filter
ICE3PCS01G
C2 a
C1 a
C1 b
D
B
C
Sigma-
Gate Driver
B
delta
ADC
CCM-PFC
2.5V
2.7V
5 May 2010
0.5V
2.5V
R
R
R
VSENSE
BVS1
BVS2
BVS3
GATE

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