ICE2PCS01XK

Manufacturer Part NumberICE2PCS01XK
ManufacturerInfineon Technologies
ICE2PCS01XK datasheet
 


Specifications of ICE2PCS01XK

Operating Supply Voltage (min)10.4VOperating Supply Voltage (max)25V
Operating Temp Range-40C to 125COperating Temperature ClassificationAutomotive
Package TypePDIPPin Count8
MountingThrough HoleLead Free Status / RoHS StatusCompliant
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3.6
Average Current Control
3.6.1
Complete Current Loop
The complete system current loop is shown in Figure
11.
L1
From
Full-wave
Retifier
R7
R2
R1
ISENSE
Current Loop
Inductor current
Current Loop
ICOMP
Compensation
OTA2
1.0mS
+/-50uA (linear range)
C3
S2
4.2V
Fault
ICE2PCS01/G
Figure 11
Complete System Current Loop
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.6.2
Current Loop Compensation
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
11). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 4.2V in the
event of IC shuts down when OLP and UVLO occur.
3.6.3
Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D
CCM PFC system is given as
V
IN
D
=
------------- -
OFF
V
OUT
Version 2.2
From the above equation, D
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D
V
. Figure 12 shows the scheme to achieve the
IN
objective.
Vout
D1
R3
C2
R4
GATE
voltage
proportional to
Gate
averaged
Driver
PWM
GATE
Comparator
Q
R
drive
C1
S
PWM Logic
Input From
Nonlinear
Figure 12
Voltage Loop
Gain
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T
kept discharged. The ramp is then allowed to rise after
T
OFFMIN
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
Figure 13 shows the timing diagrams of T
PWM waveforms.
V
CREF
V
RAMP
PWM
(1)
V
Figure 13
for a
OFF
3.6.4
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
10
ICE2PCS01/G
Functional Description
is proportional to V
OFF
, and thus to the input voltage
OFF
ave(I
) at ICOMP
ramp profile
IN
Average Current Control in CCM
(250ns typ.) and the ramp is
OFFMIN
expires. The off time of the boost transistor
.
OFF
T
OFFMIN
2.5% of T
PWM cycle
(1)
ramp
released
is a function of V
CREF
ICOMP
Ramp and PWM waveforms
Nonlinear Gain Block
09 October 2007
CCM-PFC
.
IN
t
and the
OFFMIN
t