MC9S12D64MFUE Freescale, MC9S12D64MFUE Datasheet
MC9S12D64MFUE
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MC9S12D64MFUE Summary of contents
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... Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized ...
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Revision History Version Revision Effective Number Date Date 16 NOV 19 NOV V01.00 2001 2001 18 FEB 18 FEB V01.01 2002 2002 6 MAR 6 MAR V01.02 2002 2002 4 June 4 June V01.03 2002 2002 4 July 4 July ...
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Version Revision Effective Number Date Date 20 Aug. 20 Aug. V01.06 2002 2002 20 Sept. 20 Sept. V01.07 2002 2002 25 Sept. 25 Sept. V01.08 2002 2002 10 Oct. 10 Oct. V01.09 2002 2002 8 Nov. 8 Nov. V01.10 2002 ...
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MC9S12DJ64 Device User Guide — V01.20 Version Revision Effective Number Date Date 22 July 22 July V01.15 2003 2003 24 Feb. 24 Feb. V01.16 2004 2004 21 May 21 May V01.17 2004 2004 13 July 13 July V01.18 2004 2004 ...
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Table of Contents Section 1 Introduction 1.1 Overview ...
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MC9S12DJ64 Device User Guide — V01.20 2.3.21 PH7 / KWH7 — Port H I/O Pin ...
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PS0 / RXD0 — Port S I/O Pin ...
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MC9S12DJ64 Device User Guide — V01.20 6.1 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Section 20 Port Integration Module (PIM) Block Description Section 21 Voltage Regulator (VREG) Block Description Section 22 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics A.1 General ...
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MC9S12DJ64 Device User Guide — V01.20 Appendix B Package Information B.1 General ...
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List of Figures Figure 0-1 Order Partnumber Example ...
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MC9S12DJ64 Device User Guide — V01.20 12 ...
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... EEPROM Control Register (eets1k) ........................................................42 $011C - $011F Reserved for RAM Control Register ........................................................42 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................43 $0140 - $017F CAN0 (Freescale Scalable CAN - FSCAN) ..............................................44 Table 1-3 Detailed FSCAN Foreground Receive and Transmit Buffer Layout . . . . . . . . . . .45 $0180 - $023F Reserved ..................................................................................................46 MC9S12DJ64 Device User Guide — ...
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MC9S12DJ64 Device User Guide — V01.20 $0240 - $027F PIM (Port Integration Module) ..................................................................46 $0280 - $03FF Reserved ..................................................................................................48 Table 1-4 Assigned Part ID Numbers . . . . . . . . . . . . . . . ...
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Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Generic device MC9S12DJ64 CAN0 1 J1850/BDLC 1 ...
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MC9S12DJ64 Device User Guide — V01.20 • Ports – The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5, PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0 (see Table 0-1). – The ...
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... Byte Flash (FTS64K) Block User Guide 1K Byte EEPROM (EETS1K) Block User Guide Byte Level Data Link Controller -J1850 (BDLC) Block User Guide Freescale Scalable CAN (MSCAN) Block User Guide V02 Voltage Regulator (VREG) Block User Guide Port Integration Module (PIM_9DJ64) Block User Guide MC9S12DJ64 Device User Guide — ...
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MC9S12DJ64 Device User Guide — V01.20 18 ...
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Section 1 Introduction 1.1 Overview The MC9S12DJ64 microcontroller unit (MCU 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 4K bytes of RAM, 1K bytes of EEPROM, ...
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MC9S12DJ64 Device User Guide — V01.20 – 4K byte RAM • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability • 1M bit per second, CAN 2 software compatible module – Five receive and three ...
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... Emulation Expanded Narrow Mode • Special Operating Modes – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Freescale use only) – Special Peripheral Mode (Freescale use only) Low power modes • Stop Mode • Pseudo Stop Mode • ...
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MC9S12DJ64 Device User Guide — V01.20 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DJ64 device. 22 ...
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Figure 1-1 MC9S12DJ64 Block Diagram 64K Byte Flash EEPROM 4K Byte RAM 1K Byte EEPROM VDDR VSSR VREGEN Voltage Regulator VDD1,2 VSS1,2 Single-wire Background BKGD CPU12 Debug Module XFC Clock and VDDPLL Reset PLL Periodic Interrupt VSSPLL Generation COP Watchdog ...
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MC9S12DJ64 Device User Guide — V01.20 24 ...
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... Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0) Flash Control Register EEPROM Control Register Analog to Digital Converter 10-bit 8 channels (ATD1) Freescale Scalable Can (CAN0) Reserved Port Integration Module (PIM) Reserved EEPROM array 1k Array mapped twice in the address space Fixed Flash EEPROM array incl ...
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MC9S12DJ64 Device User Guide — V01.20 Table 1-1 Device Memory Map for MC9S12DJ64 Address $C000 - $FFFF 26 Module Fixed Flash EEPROM array incl. 0.5K, 1K Protected Sector at end and 256 bytes of Vector Space at ...
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Figure 1-2 MC9S12DJ64 Memory Map out of Reset $0000 $0400 $0800 $1000 Unimplemented $4000 $8000 EXTERN $C000 $FF00 VECTORS VECTORS $FFFF EXPANDED NORMAL SINGLE CHIP MC9S12DJ64 Device User Guide — V01.20 $0000 $03FF $0000 $07FF $0000 $0FFF Unimplemented $4000 $7FFF ...
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... Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0) Flash Control Register EEPROM Control Register Analog to Digital Converter 10-bit 8 channels (ATD1) Freescale Scalable Can (CAN0) Reserved Port Integration Module (PIM) Reserved EEPROM array 1k Array mapped twice in the address space ...
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Figure 1-3 MC9S12D32 Memory Map out of Reset $0000 $0400 not usable not usable $0800 $1000 Unimplemented $4000 $8000 EXTERN $C000 $FF00 VECTORS VECTORS $FFFF EXPANDED NORMAL SINGLE CHIP MC9S12DJ64 Device User Guide — V01.20 $0000 $03FF not usable $0000 ...
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MC9S12DJ64 Device User Guide — V01.20 1.5.1 Detailed Register Map $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: Read: $0004 Reserved Write: Read: $0005 Reserved Write: Read: ...
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MMC map (HCS12 Module Mapping Control) Address Name Bit 7 Read: $0012 INITEE EE15 Write: Read: $0013 MISC Write: Read: $0014 Reserved Write: $0015 - $0016 INT map (HCS12 Interrupt) Address ...
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MC9S12DJ64 Device User Guide — V01.20 $001F - $001F Address Name Read: $001F HPRIO Write: $0020 - $0027 Address Name Read: $0020 - Reserved $0027 Write: $0028 - $002F Address Name Read: $0028 BKPCT0 Write: Read: $0029 BKPCT1 Write: Read: ...
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CRG (Clock and Reset Generator) Address Name Bit 7 Read: $0034 SYNR Write: Read: $0035 REFDV Write: Read: CTFLG $0036 TEST ONLY Write: Read: $0037 CRGFLG RTIF Write: Read: $0038 CRGINT RTIE Write: Read: $0039 CLKSEL PLLSEL ...
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MC9S12DJ64 Device User Guide — V01.20 $0040 - $007F Address Name Read: $004A TCTL3 Write: Read: $004B TCTL4 Write: Read: $004C TIE Write: Read: $004D TSCR2 Write: Read: $004E TFLG1 Write: Read: $004F TFLG2 Write: Read: $0050 TC0 (hi) Write: ...
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ECT (Enhanced Capture Timer 16 Bit 8 Channels) Address Name Bit 7 Read: $0063 PACN2 (lo) Bit 7 Write: Read: $0064 PACN1 (hi) Bit 7 Write: Read: $0065 PACN0 (lo) Bit 7 Write: Read: $0066 MCCTL MCZI ...
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MC9S12DJ64 Device User Guide — V01.20 $0040 - $007F Address Name Read: $007C TC2H (hi) Write: Read: $007D TC2H (lo) Write: Read: $007E TC3H (hi) Write: Read: $007F TC3H (lo) Write: $0080 - $009F Address Name Read: $0080 ATD0CTL0 Write: ...
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ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: Bit15 $0092 ATD0DR1H Write: Read: $0093 ATD0DR1L Write: Read: Bit15 $0094 ATD0DR2H Write: Read: $0095 ATD0DR2L Write: Read: Bit15 $0096 ATD0DR3H Write: Read: ...
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MC9S12DJ64 Device User Guide — V01.20 $00A0 - $00C7 Address Name Read: $00A9 PWMSCLB Write: Read: PWMSCNTA $00AA Test Only Write: Read: PWMSCNTB $00AB Test Only Write: Read: $00AC PWMCNT0 Write: Read: $00AD PWMCNT1 Write: Read: $00AE PWMCNT2 Write: Read: ...
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PWM (Pulse Width Modulator 8 Bit 8 Channel) Address Name Bit 7 Read: $00C2 PWMDTY6 Bit 7 Write: Read: $00C3 PWMDTY7 Bit 7 Write: Read: $00C4 PWMSDN PWMIF Write: Read: $00C5 Reserved Write: Read: $00C6 Reserved Write: ...
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MC9S12DJ64 Device User Guide — V01.20 $00D0 - $00D7 Address Name Read: $00D5 SCI1SR2 Write: Read: $00D6 SCI1DRH Write: Read: $00D7 SCI1DRL Write: $00D8 - $00DF Address Name Read: $00D8 SPI0CR1 Write: Read: $00D9 SPI0CR2 Write: Read: $00DA SPI0BR Write: ...
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BDLC (Bytelevel Data Link Controller J1850) Address Name Bit 7 Read: $00E8 DLCBCR1 IMSG Write: Read: $00E9 DLCBSVR Write: Read: $00EA DLCBCR2 SMRST Write: Read: $00EB DLCBDR Write: Read: $00EC DLCBARD Write: Read: $00ED DLCBRSR Write: Read: ...
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MC9S12DJ64 Device User Guide — V01.20 $0100 - $010F Address Name Read: $010A FDATAHI Write: Read: $010B FDATALO Write: Read: $010C - Reserved $010F Write: $0110 - $011B Address Name Read: EDIVLD $0110 ECLKDIV Write: Read: $0111 Reserved Write: Read: ...
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ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: $0120 ATD1CTL0 Write: Read: $0121 ATD1CTL1 Write: Read: $0122 ATD1CTL2 ADPU Write: Read: $0123 ATD1CTL3 Write: Read: $0124 ATD1CTL4 SRES8 Write: Read: $0125 ...
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... Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 CAN0 (Freescale Scalable CAN - FSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXACT SYNCH RXFRM CSWAI CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 RSTAT0 WUPIF ...
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... CAN0 (Freescale Scalable CAN - FSCAN) Address Name Bit 7 Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 $014F CAN0TXERR Write: Read: $0150 - CAN0IDAR0 - $0153 CAN0IDAR3 Write: Read: $0154 - CAN0IDMR0 - AM7 $0157 CAN0IDMR3 Write: Read: $0158 - CAN0IDAR4 - $015B CAN0IDAR7 Write: ...
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MC9S12DJ64 Device User Guide — V01.20 Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Extended ID Read: CAN0TIDR2 Write: $0172 Standard ID Read: Write: Extended ID Read: CAN0TIDR3 Write: $0173 Standard ID Read: Write: Read: $0174- ...
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PIM (Port Integration Module) Address Name Bit 7 Read: $024A DDRS DDRS7 Write: Read: $024B RDRS RDRS7 Write: Read: $024C PERS PERS7 Write: Read: $024D PPSS PPSS7 Write: Read: $024E WOMS WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 ...
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MC9S12DJ64 Device User Guide — V01.20 $0240 - $027F Address Name Read: $0263 RDRH Write: Read: $0264 PERH Write: Read: $0265 PPSH Write: Read: $0266 PIEH Write: Read: $0267 PIFH Write: Read: $0268 PTJ Write: Read: $0269 PTIJ Write: Read: ...
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Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-4 shows the ...
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MC9S12DJ64 Device User Guide — V01.20 50 ...
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Section 2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals built from the signal description sections of the Block Guides of the ...
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MC9S12DJ64 Device User Guide — V01.20 PWM3/KWP3/PP3 1 PWM2/KWP2/PP2 2 PWM1/KWP1/PP1 3 PWM0/KWP0/PP0 4 XADDR17/PK3 5 XADDR16/PK2 6 XADDR15/PK1 7 XADDR14/PK0 8 IOC0/PT0 9 IOC1/PT1 10 IOC2/PT2 11 IOC3/PT3 12 VDD1 13 VSS1 14 IOC4/PT4 15 IOC5/PT5 16 IOC6/PT6 17 ...
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PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12DJ64 and MC9S12D32 2.2 Signal Properties Summary Table 2-1 summarizes the pin ...
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MC9S12DJ64 Device User Guide — V01.20 Pin Name Pin Name Pin Name Function1 Function2 Function3 EXTAL — — XTAL — — RESET — — TEST — — VREGEN — — XFC — — BKGD TAGHI MODC PAD15 AN15 ETRIG1 PAD[14:08] ...
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Pin Name Pin Name Pin Name Function1 Function2 Function3 PJ7 KWJ7 SCL PJ6 KWJ6 SDA PJ[1:0] KWJ[1:0] — PK7 ECS ROMCTL PK[5:0] XADDR[19:14] — PM7 — — PM6 — — PM5 TXCAN0 SCK PM4 RXCAN0 MOSI PM3 TXCAN0 SS0 PM2 ...
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... This input only pin enables or disables the on-chip voltage regulator. 2.3.5 XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. ...
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It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device. 2.3.7 ...
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MC9S12DJ64 Device User Guide — V01.20 * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value ...
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PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin used as a MCU operating mode select pin during reset. The state of this pin is latched ...
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... PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). ...
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... PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0). MC9S12DJ64 Device User Guide — ...
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... PM0 / RXCAN0 / RXB — Port M I/O Pin 0 PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin RXB of the BDLC. 2.3.42 PP7 / KWP7 / PWM7 — Port P I/O Pin 7 PP7 is a general purpose input or output pin ...
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PP3 / KWP3 / PWM3 — Port P I/O Pin 3 PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can ...
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MC9S12DJ64 Device User Guide — V01.20 2.3.55 PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1). ...
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Pin Number Mnemonic 112-pin QFP VDDPLL 43 VSSPLL 45 VREGEN 97 2.4.1 VDDX, VSSX — Power & Ground Pins for I/O Drivers External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the ...
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MC9S12DJ64 Device User Guide — V01.20 2.4.5 VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter. 2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL Provides ...
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Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the HCS12 Core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG ...
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MC9S12DJ64 Device User Guide — V01.20 68 ...
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Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12DJ64 and MC9S12D32. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device. 4.2 ...
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MC9S12DJ64 Device User Guide — V01.20 Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS VREGEN 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: ...
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Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. ...
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MC9S12DJ64 Device User Guide — V01.20 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. 72 ...
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Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority. ...
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MC9S12DJ64 Device User Guide — V01.20 $FFCA, $FFCB Modulus Down Counter underflow $FFC8, $FFC9 Pulse Accumulator B Overflow $FFC6, $FFC7 $FFC4, $FFC5 CRG Self Clock Mode $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB $FFB8, $FFB9 $FFB6, $FFB7 ...
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NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins. 5.3.2 Memory Refer to Table ...
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Section 6 HCS12 Core Block Description 6.1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU. 6.1.1 Device-specific information When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods ...
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MC9S12DJ64 Device User Guide — V01.20 6.4 HCS12 Interrupt (INT) Block Description Consult the INT Block Guide for information on the HCS12 Interrupt module. 6.5 HCS12 Background Debug (BDM) Block Description Consult the BDM Block Guide for information on the ...
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Section 10 Analog to Digital Converter (ATD) Block Description There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DJ64. Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter module. When the ...
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... This module supports single-cycle misaligned word accesses. Section 19 MSCAN Block Description Consult the MSCAN Block User Guide for information about the Freescale Scalable CAN Module. Section 20 Port Integration Module (PIM) Block Description Consult the PIM_9DJ64 Block User Guide for information about the Port Integration Module. ...
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Table 22-1 Suggested External Component Values Component C10 / C P C11 / The PCB must ...
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MC9S12DJ64 Device User Guide — V01.20 Figure 22-1 Recommended PCB Layout 112LQFP Colpitts Oscillator VDD1 C1 VSS1 82 VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 VSSA C3 VDDA VSS2 C2 VDD2 ...
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Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator VSSX VDD1 C1 VSS1 VSSR VDDR MC9S12DJ64 Device User Guide — V01.20 C3 VSSA VDDA VSS2 C2 VDD2 Q1 VSSPLL VDDPLL R1 83 ...
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MC9S12DJ64 Device User Guide — V01.20 Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VDD1 C1 VSS1 84 VSSX VSSR R3 VDDR R2 Q1 VDDPLL R1 VSSA C3 VDDA VSS2 C2 VDD2 VSSPLL ...
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Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator VSSX VDD1 C1 VSS1 VSSR VDDR MC9S12DJ64 Device User Guide — V01.20 C3 VSSA VDDA VSS2 C2 VDD2 VSSPLL VSSPLL VDDPLL R1 85 ...
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Appendix A Electrical Characteristics A.1 General This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To ...
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MC9S12DJ64 Device User Guide — V01.20 VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used ...
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A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains ...
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MC9S12DJ64 Device User Guide — V01.20 A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body ...
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NOTE: Please refer to the temperature rating of the device ( with regards to the ambient temperature T calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Rating I/O, Regulator and Analog Supply Voltage 1 Digital Logic ...
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MC9S12DJ64 Device User Guide — V01. Ambient Temperature Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ C/W] JA The total power dissipation can be calculated from: P INT = Chip ...
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Table A-5 Thermal Package Characteristics Num C Rating 1 T Thermal Resistance LQFP112, single sided PCB Thermal Resistance LQFP112, double sided PCB with 2 internal planes 3 T Junction to Board LQFP112 4 T Junction to Case ...
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MC9S12DJ64 Device User Guide — V01.20 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage 2 P Input Low Voltage 3 C Input Hysteresis Input Leakage Current (pins in high impedance input ...
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A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed ...
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MC9S12DJ64 Device User Guide — V01.20 NOTES: 1. PLL off 2. At those low power dissipation levels can be assumed J A ...
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A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results ...
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MC9S12DJ64 Device User Guide — V01.20 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of ...
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A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted ...
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MC9S12DJ64 Device User Guide — V01.20 DNL LSB V i-1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 NOTE: ...
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A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. ...
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MC9S12DJ64 Device User Guide — V01.20 The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to ...
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A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating ...
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MC9S12DJ64 Device User Guide — V01.20 104 ...
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A.4 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL ...
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A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can ...
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MC9S12DJ64 Device User Guide — V01.20 A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal ...
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NOTES: 1. Depending on the crystal a damping series resistor might be necessary 4MHz 22pF. osc 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. Only valid if Pierce oscillator/external ...
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MC9S12DJ64 Device User Guide — V01.20 The phase detector relationship is given by the current in tracking mode. ch The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor ...
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The relative deviation its maximum for one clock period, and decreases towards zero for larger nom number of clock periods (N). Defining the jitter as For ...
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MC9S12DJ64 Device User Guide — V01.20 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Conditions are shown in Table A-4 unless otherwise ...
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A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P MSCAN Wake-up dominant pulse filtered 2 P MSCAN Wake-up dominant pulse pass MC9S12DJ64 Device User Guide — V01.20 ...
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A.7 SPI A.7.1 Master Mode Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-18 (OUTPUT) 2 SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT MISO 2 MSB ...
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MC9S12DJ64 Device User Guide — V01. (OUTPUT SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT) 5 MISO MSB IN (INPUT) 9 MOSI PORT DATA MASTER MSB OUT (OUTPUT configured as output 2. LSBF ...
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A.7.2 Slave Mode Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-19. SS (INPUT) SCK (CPOL 0) (INPUT) 2 SCK (CPOL 1) (INPUT) 7 MISO MSB OUT SLAVE (OUTPUT) 5 MOSI MSB ...
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MC9S12DJ64 Device User Guide — V01.20 Table A-19 SPI Slave Mode Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs Num C Rating 1 P Operating Frequency P SCK Period t = ...
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A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-20. All major bus signals are included in the diagram. While both a data write ...
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MC9S12DJ64 Device User Guide — V01.20 ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 IPIPO0 IPIPO1, PE6,5 Figure ...
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Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 1 P Frequency of operation (E-clock Cycle time 3 D Pulse width, E low Pulse width, ...
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MC9S12DJ64 Device User Guide — V01.20 Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 32 D NOACC hold time 33 D IPIPO[1:0] delay time D IPIPO[1:0] valid time to ...
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Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DJ64 and MC9S12D32 packages. MC9S12DJ64 Device User Guide — V01.20 123 ...
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MC9S12DJ64 Device User Guide — V01.20 B.2 112-pin LQFP package 0. PIN 1 112 IDENT 1 VIEW 0.050 C1 VIEW AB Figure B-1 112-pin LQFP mechanical ...
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B.3 80-pin QFP package 0.20 M 0.05 A-B 0. -C- H SEATING PLANE G DATUM -H- PLANE W X DETAIL C Figure B-2 80-pin QFP Mechanical Dimensions (case no. 841B) L ...
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User Guide End Sheet MC9S12DJ64 Device User Guide — V01.20 127 ...
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MC9S12DJ64 Device User Guide — V01.20 128 FINAL PAGE OF 128 PAGES ...