MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet

MC9S08JM60CLH

Manufacturer Part Number
MC9S08JM60CLH
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S08JM60CLH

Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant

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MC9S08JM60
MC9S08JM32
Data Sheet
HCS08
Microcontrollers
MC9S08JM60
Rev. 3
1/2009
freescale.com

Related parts for MC9S08JM60CLH

MC9S08JM60CLH Summary of contents

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... MC9S08JM60 MC9S08JM32 Data Sheet HCS08 Microcontrollers MC9S08JM60 Rev. 3 1/2009 freescale.com ...

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MC9S08JM60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • 48-MHz HCS08 CPU (central processor unit) • 24-MHz internal bus frequency • HC08 instruction set with added BGND instruction • Background debugging system • Breakpoint capability to allow single breakpoint ...

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MC9S08JM60 Series Data Sheet Covers MC9S08JM60 MC9S08JM32 MC9S08JM60 Rev. 3 1/2009 ...

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... This product incorporates SuperFlash Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. Description of Changes Initial release Changed the location connect to EXTAL in S Changed port rise and fall time in ...

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... Chapter 15 16-Bit Serial Peripheral Interface (S08SPI16V1 243 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3 271 Chapter 17 Universal Serial Bus Device Controller (S08USBV1 295 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Appendix A Electrical Characteristics 349 Appendix B Ordering Information and Mechanical Drawings 373 Freescale Semiconductor List of Chapters Title MC9S08JM60 Series Data Sheet, Rev. 3 Page 7 ...

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... On-Chip Peripheral Modules in Stop Modes ....................................................................39 4.1 MC9S08JM60 Series Memory Map ...............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42 4.2 Register Addresses and Bit Assignments ........................................................................................43 4.3 RAM (System RAM) ......................................................................................................................50 4.4 USB RAM .......................................................................................................................................51 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections , ...

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... System Device Identification Register (SDIDH, SDIDL) ................................................76 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................77 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................78 6.1 Introduction .....................................................................................................................................81 6.2 Port Data and Data Direction ..........................................................................................................81 10 Chapter 5 Chapter 6 Parallel Input/Output MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Indexed Addressing Mode ..............................................................................................104 7.4 Special Operations .........................................................................................................................105 7.4.1 Reset Sequence ...............................................................................................................105 7.4.2 Interrupt Sequence ..........................................................................................................105 7.4.3 Wait Mode Operation ......................................................................................................106 7.4.4 Stop Mode Operation ......................................................................................................106 7.4.5 BGND Instruction ...........................................................................................................107 7.5 HCS08 Instruction Set Summary ..................................................................................................108 Freescale Semiconductor Chapter 7 MC9S08JM60 Series Data Sheet, Rev ...

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... Voltage Reference Low (V 10.2.5 Analog Channel Inputs (ADx) ........................................................................................141 10.3 Register Definition ........................................................................................................................141 10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................141 12 Chapter 8 Chapter 9 Keyboard Interrupt (S08KBIV2) Chapter 10 ) ..................................................................................................141 DDAD ) .................................................................................................141 SSAD ) ...................................................................................141 REFH ) ....................................................................................141 REFL MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... IIC Data I/O Register (IICD) ..........................................................................................169 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................170 11.4 Functional Description ..................................................................................................................171 11.4.1 IIC Protocol .....................................................................................................................171 11.4.2 10-bit Address .................................................................................................................174 11.4.3 General Call Address ......................................................................................................175 11.5 Resets ............................................................................................................................................175 Freescale Semiconductor Chapter 11 MC9S08JM60 Series Data Sheet, Rev ...

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... RTC Status and Control Register (RTCSC) ....................................................................217 13.3.2 RTC Counter Register (RTCCNT) ..................................................................................218 13.3.3 RTC Modulo Register (RTCMOD) ................................................................................218 13.4 Functional Description ..................................................................................................................218 13.4.1 RTC Operation Example .................................................................................................219 13.5 Initialization/Application Information ..........................................................................................220 14 Chapter 12 Chapter 13 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... SPI Data Registers (SPIxDH:SPIxDL) ...........................................................................254 15.3.6 SPI Match Registers (SPIxMH:SPIxML) .......................................................................255 15.4 Functional Description ..................................................................................................................256 15.4.1 General ............................................................................................................................256 15.4.2 Master Mode ...................................................................................................................256 15.4.3 Slave Mode .....................................................................................................................257 15.4.4 Data Transmission Length ..............................................................................................258 Freescale Semiconductor Chapter 14 Chapter 15 MC9S08JM60 Series Data Sheet, Rev ...

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... Current Consumption in USB Suspend ..........................................................................295 17.1.3 3.3 V Regulator ...............................................................................................................295 17.1.4 Features ...........................................................................................................................298 17.1.5 Modes of Operation ........................................................................................................298 17.1.6 Block Diagram ................................................................................................................299 17.2 External Signal Description ..........................................................................................................300 17.2.1 USBDP ............................................................................................................................300 17.2.2 USBDN ...........................................................................................................................300 16 Chapter 16 Chapter 17 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Hardware Breakpoints ....................................................................................................341 18.4 Register Definition ........................................................................................................................341 18.4.1 BDC Registers and Control Bits .....................................................................................341 18.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................343 18.4.3 DBG Registers and Control Bits .....................................................................................344 Freescale Semiconductor Chapter 18 Development Support MC9S08JM60 Series Data Sheet, Rev ...

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... A.14 USB Electricals ..............................................................................................................................370 A.15 EMC Performance..........................................................................................................................370 A.15.1 Radiated Emissions..........................................................................................................370 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................373 B.2 Orderable Part Numbering System ................................................................................................373 B.3 Mechanical Drawings.....................................................................................................................373 18 Appendix A Electrical Characteristics Appendix B MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... ADC IIC IRQ KBI SCI1 SCI2 SPI1 SPI2 TPM1 TPM2 USB I/O pins Package types 1.2 MCU Block Diagram The block diagram in Figure 1-1 Freescale Semiconductor Device MC9S08JM60 64-pin 48-pin 44-pin 64-pin 60,912 4096 256 yes 12-ch 8-ch 8-ch yes yes 8 ...

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... PTB0/MISO2/ADP0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2 PTC1/SDA PTC0/SCL PTD7 PTD6 PTD5 PTD4/ADP11 PTD3/KBIP3/ADP10 PTD2/KBIP2/ACMPO PTD1/ADP9/ACMP– PTD0/ADP8/ACMP+ PTE7/SS1 PTE6/SPSCK1 PTE5/MOSI1 PTE4/MISO1 PTE3/TPM1CH1 PTE2/TPM1CH0 4 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 4 PTF1/TPM1CH3 PTF0/TPM1CH2 4 PTG5/EXTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

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... Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. All memory mapped registers associated with the modules are clocked with BUSCLK. Freescale Semiconductor Table 1-2. Versions of On-Chip Modules Module ...

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... Chapter 13, “Real-Time Counter MC9S08JM60 Series Data Sheet, Rev. 3 IIC SCI1 SCI2 SPI1 3 2 RAM Flash ADC (S08ADC12V1),” Appendix A, “Electrical Characteristics,” for (S08MCGV1),” explains the (S08RTCV1),” for more Clock,” explains the (S08RTCV1),” and Chapter 10, Freescale Semiconductor SPI2 ...

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... TPMCLK — TPMCLK is the optional external clock source for the TPM modules. The TPMCLK must be limited to 1/4th the frequency of the BUSCLK for synchronization. See “Timer/Pulse-Width Modulator Freescale Semiconductor (S08ADC12V1),” for more information regarding the use of (S08RTCV1),” and Watchdog,” for details on using the LPO clock with these modules. ...

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... Chapter 1 Device Overview 24 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes pinout diagrams, a table of signal properties, and detailed discussion of signals. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev ...

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... PTF6 12 PTE0/TxD1 13 PTE1/RxD1 14 PTE2/TPM1CH0 15 PTE3/TPM1CH1 Figure 2-1. MC9S08JM60 in 64-Pin QFP/LQFP Package 64-Pin QFP/LQFP MC9S08JM60 Series Data Sheet, Rev PTD2/KBIP2/ACMPO SSAD 46 V REFL 45 V REFH 44 V DDAD 43 PTD1/ADP9/ACMP– 42 PTD0/ADP8/ACMP+ 41 PTB7/ADP7 40 PTB6/ADP6 39 PTB5/KBIP5/ADP5 38 PTB4/KBIP4/ADP4 37 PTB3/SS2/ADP3 PTB2/SPSCK2/ADP2 36 35 PTB1/MOSI2/ADP1 34 PTB0/MISO2/ADP0 PTA5 Freescale Semiconductor ...

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... PTC4 1 IRQ/TPMCLK 2 RESET 3 PTF0/TPM1CH2 4 PTF1/TPM1CH3 5 PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 8 PTF6 PTE0/TxD1 9 PTE1/RxD1 10 PTE2/TPM1CH0 11 PTE3/TPM1CH1 12 13 Figure 2-2. MC9S08JM60 Series in 48-Pin QFN Package Freescale Semiconductor 48-Pin QFN MC9S08JM60 Series Data Sheet, Rev. 3 Chapter 2 Pins and Connections 37 38 PTD2/KBIP2/ACMPO SSAD REFL DDAD REFH 33 PTD1/ADP9/ACMP– ...

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... Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08JM60 series application systems 44-Pin LQFP MC9S08JM60 Series Data Sheet, Rev PTD2/KBIP2/ACMPO SSAD REFL DDAD REFH 30 PTD1/ADP9/ACMP– 29 PTD0/ADP8/ACMP+ PTB5/KBIP5/ADP5 28 PTB4/KBIP4/ADP4 27 26 PTB3/SS2/ADP3 PTB2/SPSCK2/ADP2 25 PTB1/MOSI2/ADP1 24 PTB0/MISO2/ADP0 Freescale Semiconductor ...

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... USB only. The diagram shows a configuration where the on-chip regulator and R PUDP The voltage regulator output is used for 5.0-V supply from upstream port that can be used for USB operation BUS 6. USBDP and USBDN are powered by the 3.3-V regulator or external 3.3-V supply on V Freescale Semiconductor V REFH MC9S08JM60 V DDAD C BYAD 0.1 μ ...

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... PCB capacitance for each oscillator pin (EXTAL and XTAL SSOSC DDAD SSAD USB33 MC9S08JM60 Series Data Sheet, Rev USB33 and pin. This pin SSOSC pin through a low-impedance SS maintains an output voltage of 3.3 V and Chapter 12, “Multi-Purpose Clock Freescale Semiconductor power ...

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... The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin can be used for TPMCLK. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See an example. Freescale Semiconductor , V ) REFH REFL MC9S08JM60 Series Data Sheet, Rev ...

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... For information about how and when on-chip peripheral systems use these pins, see the appropriate module chapter. Immediately after reset, all pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. 32 MC9S08JM60 Series Data Sheet, Rev available. PUDP Chapter 6, “Parallel Freescale Semiconductor ...

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... RxD1 PTE2 TPM1CH0 PTE3 TPM1CH1 PTE4 MISO1 PTE5 MOSI1 PTE6 SPSCK1 PTE7 SS1 PTG0 KBIP0 PTG1 KBIP1 28 24 PTA0 29 PTA1 30 PTA2 31 PTA3 32 PTA4 Freescale Semiconductor Pin Number 64 48 Alt2 TPMCLK 35 27 RESET — 41 — — 50 — 51 — 52 — USBDN 56 40 USBDP ...

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... Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module recommended that all modules that share a pin be disabled before enabling another module. 34 NOTE Table 2-1 illustrates the priority if multiple modules MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev ...

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... MCU is operated in run mode for the first time. When the MC9S08JM60 series is shipped from the Freescale factory, the flash program memory is erased by default unless specifically noted, so there is no program that could be executed in run mode until the flash memory is initially programmed ...

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... For the ADC to operate, the LVD must be left enabled when entering stop3. For the ACMP to operate when ACGBS in ACMPSC is set, the LVD must be left enabled when entering stop3. For the XOSC to operate with an external reference when RANGE in MCGC2 is set, the LVD must be left enabled when entering stop3. Freescale Semiconductor Table 3-1. Stop Mode Selection LVDSE PPDC ...

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... For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before 38 Support.” If ENBDM is set when the CPU executes a NOTE MC9S08JM60 Series Data Sheet, Rev. 3 Table 3-1. Most is below the LVD DD Freescale Semiconductor ...

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... ERCLKEN and EREFSTEN set in MCGC2, else in standby. For high frequency range (RANGE in MCGC2 set) requires the LVD to also be enabled in stop3. 6 USBEN in CTL is set and USBPHYEN in USBCTL0 is set, else off. Freescale Semiconductor Mode,” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Mode ...

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... Chapter 3 Modes of Operation 40 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x00AF) • High-page registers (0x1800 through 0x185F) • Nonvolatile registers (0xFFB0 through 0xFFBF) Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev ...

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... Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08JM60 series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Interrupts, and System Configuration.” ...

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... This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in flash memory at 0xFFB0–0xFFBF. Nonvolatile register locations include: — Three values which are loaded into working registers at reset Freescale Semiconductor Vector ADC Conversion KBI SCI2 Transmit SCI2 Receive ...

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... Table 4-4, the whole address in column one is shown in bold. In 4-4, the register names in column two are shown in bold to set them apart MC9S08JM60 Series Data Sheet, Rev. 3 Table 4 summary of all Freescale Semiconductor ...

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... TPM1MODH Bit 15 0x0024 TPM1MODL Bit 7 0x0025 TPM1C0SC CH0F 0x0026 TPM1C0VH Bit 15 0x0027 TPM1C0VL Bit 7 0x0028 TPM1C1SC CH1F 0x0029 TPM1C1VH Bit 15 Freescale Semiconductor — PTAD5 PTAD4 — PTADD5 PTADD4 PTBD6 PTBD5 PTBD4 PTBDD6 PTBDD5 PTBDD4 PTCD6 PTCD5 PTCD4 PTCDD6 PTCDD5 PTCDD4 ...

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... IRCLKEN LP EREFS ERCLKEN EREFSTEN CLKST OSCINIT VDIV — — — CPOL CPHA SSOE BIDIROE 0 SPISWAI 0 SPR2 SPR1 Freescale Semiconductor Bit 0 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 ...

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... SPI2S SPRF 0x0074 SPI2DH Bit 15 0x0075 SPI2DL Bit 7 0x0076 SPI2MH Bit 15 0x0077 SPI2ML Bit 7 0x0078– Reserved — 0x007F 0x0080 USBCTL0 USBRESET 0x0081– Reserved — 0x0087 0x0088 PERID 0 Freescale Semiconductor AD6 AD5 AD4 IICIE MST TX IAAS BUSY ARBL DATA ADEXT 0 0 — ...

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... ID11 ID10 ID9 ID3 ID2 ID1 — — — 1 LVDSE LVDE 0 PPDF PPDACK — — — — Freescale Semiconductor Bit 0 NID0 REV0 — USBRSTF USBRST PIDERRF PIDERR 0 USBEN ADDR0 FRM0 FRM8 — EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK — ...

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... PTDPE PTDPE7 0x184D PTDSE PTDSE7 0x184E PTDDS PTDDS7 0x184F Reserved — 0x1850 PTEPE PTEPE7 0x1851 PTESE PTESE7 0x1852 PTEDS PTEDS7 0x1853 Reserved — 0x1854 PTFPE PTFPE7 0x1855 PTFSE PTFSE7 0x1856 PTFDS PTFDS7 Freescale Semiconductor ARM TAG BRKEN BEGIN ARMF 0 — — ...

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... MC9S08JM60 Series Data Sheet, Rev — — — PTGPE3 PTGPE2 PTGPE1 PTGPE0 PTGSE3 PTGSE2 PTGSE1 PTGSE0 PTGDS3 PTGDS2 PTGDS1 PTGDS0 — — — — — — FPS3 FPS2 FPS1 — — — SEC01 Freescale Semiconductor Bit 0 — — Bit 0 FTRIM — FPDIS — SEC00 ...

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... MC9S08JM60 series usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX #RamLast+1 ...

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... Table 4-5. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 NOTE MC9S08JM60 Series Data Sheet, Rev between 150 kHz and 200 kHz FCLK . The times are shown as a number = 5 μs. Program and erase times Time if FCLK = 200 kHz 45 μs 20 μ 100 ms Freescale Semiconductor ...

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... The FCDIV register must be initialized before using any flash commands. This only must be done once following a reset. FLASH PROGRAM AND ERASE FLOW Figure 4-2. Flash Program and Erase Flowchart Freescale Semiconductor is a flowchart for executing all of the commands except for burst (Note 1) Note 1: Required only once after reset. WRITE TO FCDIV ...

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... This is because the high voltage to the array must be disabled and then enabled again new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. 54 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Writing to a flash address while FCBEF is not set (A new command cannot be started until the command buffer is empty.) • Writing a second time to a flash address before launching the previous command (There is only one write to flash for every command.) Freescale Semiconductor (Note 1) WRITE TO FCDIV START 0 ...

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... One use for block protection is to block protect an area of flash memory for a bootloader program. This bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the 56 NVPROT).”) 1 A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism MC9S08JM60 Series Data Sheet, Rev. 3 Section 4.7.4, “Flash Freescale Semiconductor ...

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... BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Chapter 4 Memory ...

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... There is also an 8-byte comparison key in flash memory. Refer to absolute address assignments for all flash registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 58 MC9S08JM60 Series Data Sheet, Rev ...

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... The automated programming logic uses an integer number of these pulses to complete an erase or program operation. See Equation if PRDIV8 = 0 — PRDIV8 = 1 — f Table 4-7 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies. Freescale Semiconductor DIV5 DIV4 DIV3 0 ...

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... Min, 6.7 μs Max) FCLK 5 μs 200 kHz 5.2 μs 192.3 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 5 μs 200 kHz 6.7 μs 150 kHz SEC01 “Security.” Table Freescale Semiconductor 0 SEC00 4-9. When ...

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... R FPS7 FPS6 (1) (1) W Reset This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. Flash Protection Register (FPROT) Freescale Semiconductor Table 4-9. Security States Description 0:0 0:1 1:0 unsecured 1 ...

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... FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. 62 Description FPVIOL FACCERR Figure 4-9. Flash Status Register (FSTAT) Description MC9S08JM60 Series Data Sheet, Rev FBLANK Freescale Semiconductor ...

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... Command Blank check Byte program Byte program — burst mode Page erase (512 bytes/page) Mass erase (all flash) All other command codes are illegal and generate an access error. Freescale Semiconductor Description Section 4.5.5, “Access Execution,” for a detailed discussion of flash programming ...

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... Chapter 4 Memory It is not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. 64 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Low-voltage detect (LVD) • Computer operating properly (COP) timer • Illegal opcode detect (ILOP) • Background debug forced reset • External reset pin (RESET) • Clock generator loss of lock and loss of clock reset (LOC) Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Table 5-1) 65 ...

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... Section 5.7.4, “System Options Register 1 Section 5.7.5, “System Options Register 2 Table 5-6 summaries the control functions of the COPCLKS and MC9S08JM60 Series Data Sheet, Rev. 3 (SOPT1),” (SOPT2),” for additional Freescale Semiconductor ...

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... RTI that is used to return from the ISR. When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-1). Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE MC9S08JM60 Series Data Sheet, Rev ...

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... CONDITION CODE REGISTER ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08JM60 Series Data Sheet, Rev AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...

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... Vkeyboard 24 0xFFCE:FFCF Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration NOTE DD – 0.7 V. The internal gates connected to this pin are pulled . DD Module Source Unused vector space (available for user program) Vrtc System RTIF control Viic ...

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... TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 — — STALL USB Status RESUME SLEEP TOKDNE SOFTOK ERROR USBRST SPIE SPI2 SPIE SPTIE SPMIE SPIE SPI1 SPIE SPTIE SPMIE LOLIE MCG loss of lock LVWIE Low-voltage detect IRQIE IRQ pin Freescale Semiconductor ...

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... The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is approaching the low voltage condition. When a low voltage warning condition is detected and is configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt request will occur. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Module Source ...

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... Refer to the direct-page register summary in address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “ ...

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... External Reset Pin — Reset was caused by an active-low level on the external reset pin. PIN 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description Sensitivity,” for more details. ...

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... This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT 74 Description Description MC9S08JM60 Series Data Sheet, Rev BDFR Freescale Semiconductor ...

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... Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode (COPW = 1). 2 Values shown in milliseconds based on t tolerance of this value. Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration ...

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... This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU — — Reset = Unimplemented or Reserved Figure 5-7. System Device Identification Register — High (SDIDH Description ID11 — — 0 MC9S08JM60 Series Data Sheet, Rev SPI1FE SPI2FE ACIC ID10 ID9 ID8 Freescale Semiconductor ...

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... LVWF will be set in the case when V 2 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1) Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description 5 4 ID5 ...

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... Any other Reset Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2) 78 Description PPDF LVDV LVWV Unaffected by reset MC9S08JM60 Series Data Sheet, Rev PPDC PPDACK Freescale Semiconductor ...

Page 79

... Stop3 mode enabled. 1 Stop2, partial power down, mode enabled. Table 5-12. LVD and LVW trip point typical values LVDV:LVWV 0:0 0:1 1:0 1:1 1 See Appendix A, “Electrical Freescale Semiconductor Chapter 5 Resets, Interrupts, and System Configuration Description Table 5-12. LVW Trip Point V = 2.74 V LVW0 V = 2.92 V ...

Page 80

... Chapter 5 Resets, Interrupts, and System Configuration 80 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 81

... Reading and writing of parallel I/O is done through the port data registers. The direction, input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram below. Freescale Semiconductor Chapter 2, “Pins and Table 2-1 ...

Page 82

... I/O pins. The pin control registers operate independently of the parallel I/O registers. 82 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram MC9S08JM60 Series Data Sheet, Rev. 3 Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...

Page 83

... This section provides information about the registers associated with the parallel I/O ports and pin control functions. These parallel I/O registers are located in page zero of the memory map and the pin control registers are located in the high page register section of memory. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Chapter 6 Parallel Input/Output ...

Page 84

... Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin control registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.5.1 Port A I/O Registers (PTAD and PTADD) Port A parallel I/O function is controlled by the registers listed below ...

Page 85

... Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high PTADS[5:0] output drive for the associated PTA pin. 0 Low output drive enabled for port A bit n. 1 High output drive enabled for port A bit n. Freescale Semiconductor PTAPE5 ...

Page 86

... In addition to the I/O control, port B pins are controlled by the registers listed below PTBD5 PTBD4 PTBD3 0 0 Figure 6-7. Port B Data Register (PTBD) Table 6-6. PTBD Register Field Descriptions Description 5 4 PTBDD5 PTBDD4 PTBDD3 0 0 Description MC9S08JM60 Series Data Sheet, Rev PTBD2 PTBD1 PTBDD2 PTBDD1 Freescale Semiconductor 0 PTBD0 0 0 PTBDD0 0 ...

Page 87

... Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high PTBDS[7:0] output drive for the associated PTB pin. 0 Low output drive enabled for port B bit n. 1 High output drive enabled for port B bit n. Freescale Semiconductor PTBPE5 ...

Page 88

... Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) In addition to the I/O control, port C pins are controlled by the registers listed below PTCD5 PTCD4 PTCD3 Figure 6-12. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description MC9S08JM60 Series Data Sheet, Rev PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...

Page 89

... Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high PTCDS[6:0] output drive for the associated PTC pin. 0 Low output drive enabled for port C bit n. 1 High output drive enabled for port C bit n. Freescale Semiconductor PTCPE5 ...

Page 90

... Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) In addition to the I/O control, port D pins are controlled by the registers listed below PTDD5 PTDD4 PTDD3 Figure 6-17. Port D Data Register (PTDD) Description PTDDD5 PTDDD4 PTDDD3 Description MC9S08JM60 Series Data Sheet, Rev PTDD2 PTDD1 PTDD0 PTDDD2 PTDDD1 PTDDD0 Freescale Semiconductor ...

Page 91

... Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high PTDDS[7:0] output drive for the associated PTD pin. 0 Low output drive enabled for port D bit n. 1 High output drive enabled for port D bit n. Freescale Semiconductor PTDPE5 ...

Page 92

... Port E Pin Control Registers (PTEPE, PTESE, PTEDS) In addition to the I/O control, port E pins are controlled by the registers listed below PTED5 PTED4 PTED3 Figure 6-22. Port E Data Register (PTED) Description PTEDD5 PTEDD4 PTEDD3 Description MC9S08JM60 Series Data Sheet, Rev PTED2 PTED1 PTED0 PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...

Page 93

... Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high PTEDS[7:0] output drive for the associated PTE pin. 0 Low output drive enabled for port E bit n. 1 High output drive enabled for port E bit n. Freescale Semiconductor PTEPE5 ...

Page 94

... Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) In addition to the I/O control, port F pins are controlled by the registers listed below PTFD5 PTFD4 PTFD3 Figure 6-27. Port F Data Register (PTFD) Description PTFDD5 PTFDD4 PTFDD3 Description MC9S08JM60 Series Data Sheet, Rev PTFD2 PTFD1 PTFD0 PTFDD2 PTFDD1 PTFDD0 Freescale Semiconductor ...

Page 95

... Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high PTFDS[7:0] output drive for the associated PTF pin. 0 Low output drive enabled for port F bit n. 1 High output drive enabled for port F bit n. Freescale Semiconductor PTFPE5 ...

Page 96

... Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) In addition to the I/O control, port G pins are controlled by the registers listed below PTGD5 PTGD4 PTGD3 Figure 6-32. Port G Data Register (PTGD) Description PTGDD5 PTGDD4 PTGDD3 Description MC9S08JM60 Series Data Sheet, Rev PTGD2 PTGD1 PTGD0 PTGDD2 PTGDD1 PTGDD0 Freescale Semiconductor ...

Page 97

... Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high PTGDSn output drive for the associated PTG pin. 0 Low output drive enabled for port G bit n. 1 High output drive enabled for port G bit n. Freescale Semiconductor PTGPE5 ...

Page 98

... Chapter 6 Parallel Input/Output 98 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 99

... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...

Page 100

... X. 100 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 101

... Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code bits in general terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. ...

Page 102

... No carry out of bit 7 1 Carry out of bit 7 102 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 103

... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Chapter 7 Central Processor Unit (S08CPUV2) ...

Page 104

... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 104 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 105

... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the Freescale Semiconductor Resets, Interrupts, and System Configuration MC9S08JM60 Series Data Sheet, Rev. 3 ...

Page 106

... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation 106 chapter for more details. MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 107

... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Chapter 7 Central Processor Unit (S08CPUV2) ...

Page 108

... rpp prpp prpp 0 – – rpp 3 F4 rfp pprpp prpp rfwpp rfwpp 4 78 rfwp prfwpp rfwpp rfwpp 4 77 rfwp prfwpp 3 – – – – – – ppp Freescale Semiconductor Affect on CCR – – – – – – – ...

Page 109

... BLT rel BMC rel Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( BPL rel Branch if Plus ( Freescale Semiconductor Operation Object Code DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) ...

Page 110

... AD rr ssppp rpppp pppp pppp – – – – – – rpppp rfppp prpppp 1 – – – – – – – 0 – – – rfwpp – – – rfwpp 4 7F rfwp prfwpp Freescale Semiconductor Affect on CCR ...

Page 111

... A ← (H:A)÷(X); H ← Remainder EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP Freescale Semiconductor Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 M ← (M)= $FF – (M) ...

Page 112

... AE prrfp pprrpp prrpp prrpp rpp prpp prpp 0 – – rpp 3 FE rfp pprpp prpp rfwpp rfwpp 4 78 rfwp prfwpp rfwpp rfwpp 4 74 rfwp prfwpp Freescale Semiconductor Affect on CCR – – – – – – – – – – 0 ...

Page 113

... ROLX C ROL oprx8,X b7 ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8,X b7 ROR ,X ROR oprx8,SP Freescale Semiconductor Operation Object Code DIR/DIR DIR/IX+ source IMM/DIR IX+/DIR INH M ← – (M) = $00 – (M) DIR INH X ← – (X) = $00 – (X) INH M ← ...

Page 114

... B7 dd wpp pwpp pwpp 3 0 – wpp ppwpp pwpp wwpp 5 0 – pwwpp pwwpp 2 – – 0 – – – 8E fp... wpp pwpp pwpp 3 0 – wpp ppwpp pwpp Freescale Semiconductor Affect on CCR – – – – – – – – ...

Page 115

... TST opr8a Test for Negative or Zero TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) Freescale Semiconductor Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 INH INH ...

Page 116

... Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: Set or cleared – Not affected U Undefined MC9S08JM60 Series Data Sheet, Rev. 3 Affect Cyc-by-Cyc on CCR Details – – – – – – – – 0 – – – 8F fp... Freescale Semiconductor ...

Page 117

... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...

Page 118

... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...

Page 119

... The ACMP module can be configured to connect the output of the analog comparator to TPM input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPM1CH0 pin is not available externally regardless of the configuration of the TPM module. Freescale Semiconductor NOTE Section 5.7.7, “System Power Management Status and Control 1 MC9S08JM60 Series Data Sheet, Rev. 3 Appendix A.6, “ ...

Page 120

... SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 TPM1CHx 4 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 PTF7 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 KBIPx 4 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 121

... ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 8.1.5 Block Diagram The block diagram for the Analog Comparator module is shown Freescale Semiconductor Figure MC9S08JM60 Series Data Sheet, Rev. 3 Analog Comparator (S08ACMPV2) 8-2. ...

Page 122

... Analog Comparator (S08ACMPV2) Internal Reference ACMP+ ACMP- Figure 8-2. Analog Comparator 5V (ACMP5) Block Diagram 122 Internal Bus ACBGS Status & Control ACME Register + Interrupt Control - Comparator MC9S08JM60 Series Data Sheet, Rev. 3 ACMP INTERRUPT REQUEST ACIE ACF ACOPE ACMPO Freescale Semiconductor ...

Page 123

... Refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all ACMP registers.This section refers to registers and control bits only by their names. Some MCUs may have more than one ACMP, so register names include placeholder characters to identify which ACMP is being referenced. Freescale Semiconductor Table 8-1. Table 8-1. Signal Properties Function Inverting analog input to the ACMP ...

Page 124

... Analog Comparator Mode — ACMOD selects the type of compare event which sets ACF. ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge 124 ACO ACF ACIE Description MC9S08JM60 Series Data Sheet, Rev ACOPE ACMOD Freescale Semiconductor ...

Page 125

... The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPO pin using ACOPE. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Analog Comparator (S08ACMPV2) ...

Page 126

... Analog Comparator (S08ACMPV2) 126 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 127

... Connections,” for more information about the logic and hardware aspects of these pins. MC9S08JM60 series devices operate at a higher voltage range (2 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. Freescale Semiconductor NOTE MC9S08JM60 Series Data Sheet, Rev. 3 Chapter 2, “Pins ...

Page 128

... PTB0/MISO2/ADP0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2 PTC1/SDA PTC0/SCL PTD7 PTD6 PTD5 PTD4/ADP11 PTD3/KBIP3/ADP10 PTD2/KBIP2/ACMPO PTD1/ADP9/ACMP– PTD0/ADP8/ACMP+ PTE7/SS1 PTE6/SPSCK1 PTE5/MOSI1 PTE4/MISO1 PTE3/TPM1CH1 PTE2/TPM1CH0 4 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 4 PTF1/TPM1CH3 PTF0/TPM1CH2 4 PTG5/EXTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 129

... KBI in Active Background Mode When the microcontroller is in active background mode, the KBI will continue to operate normally. 9.1.3 Block Diagram The block diagram for the keyboard interrupt module is shown Freescale Semiconductor Figure MC9S08JM60 Series Data Sheet, Rev. 3 Keyboard Interrupts (S08KBIV2) Modes of Operation 9-2 ...

Page 130

... Figure 9-2. KBI Block Diagram Table 9-1. Table 9-1. Signal Properties Function Keyboard interrupt pins Memory chapter for the absolute address assignments for MC9S08JM60 Series Data Sheet, Rev. 3 BUSCLK KBF SYNCHRONIZER STOP BYPASS KBI STOP INTERRUPT REQUES T KBIE I/O I Freescale Semiconductor ...

Page 131

... Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. KBIPEn 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 9.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. Freescale Semiconductor KBF 0 0 Figure 9-3 ...

Page 132

... A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing KBACK in 132 KBEDG5 KBEDG4 KBEDG3 Figure 9-5. KBI Edge Select Register Description MC9S08JM60 Series Data Sheet, Rev KBEDG2 KBEDG1 KBEDG0 Freescale Semiconductor ...

Page 133

... If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Keyboard Interrupts (S08KBIV2) 133 ...

Page 134

... Keyboard Interrupts (S08KBIV2) 134 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 135

... This section provides information for configuring the ADC on this device. 10.1.1.1 Channel Assignments The ADC channel assignments for the MC9S08JM60 Series devices are shown in the table below. Reserved channels convert to an unknown value. Freescale Semiconductor NOTE MC9S08JM60 Series Data Sheet, Rev. 3 135 ...

Page 136

... Reserved AD24 Reserved AD25 Reserved AD26 Temperature 1 Sensor AD27 Internal Bandgap Reserved V V REFH REFH V V REFL REFL module None disabled Appendix A.8, Freescale Semiconductor N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ...

Page 137

... Low-Power Mode Operation The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set. Freescale Semiconductor Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ) ÷ m) – V TEMP TEMP25 and m values from the ADC Electricals table ...

Page 138

... SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 TPM1CHx 4 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 PTF7 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 KBIPx 4 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 139

... Selectable asynchronous hardware conversion trigger • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value • Temperature sensor 10.1.4 ADC Module Block Diagram Figure 10-2 provides a block diagram of the ADC module Freescale Semiconductor . MC9S08JM60 Series Data Sheet, Rev. 3 Analog-to-Digital Converter (S08ADC12V1) 139 ...

Page 140

... Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD MC9S08JM60 Series Data Sheet, Rev. 3 Async Clock Gen ADACK Bus Clock ÷2 ALTCLK AIEN 1 Interrupt COCO 2 3 Freescale Semiconductor ...

Page 141

... Status and Control Register 1 (ADCSC1) This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...

Page 142

... ADCO Table 10-3. ADCSC1 Field Descriptions Description Table 10-4. Input Channel Select ADCH Input Select 00000–01111 AD0–15 10000–11011 AD16–27 11100 Reserved 11101 V REFH 11110 V REFL 11111 Module disabled MC9S08JM60 Series Data Sheet, Rev ADCH Freescale Semiconductor ...

Page 143

... ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL. Freescale Semiconductor 5 4 ...

Page 144

... Reset Figure 10-7. Compare Value High Register (ADCCVH) 144 ADR11 ADR5 ADR4 ADR3 ADCV11 MC9S08JM60 Series Data Sheet, Rev ADR10 ADR9 ADR8 ADR2 ADR1 ADR0 ADCV10 ADCV9 ADCV8 Freescale Semiconductor ...

Page 145

... Longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 Short sample time 1 Long sample time Freescale Semiconductor ADCV5 ...

Page 146

... Selected Clock Source Bus clock Bus clock divided by 2 Alternate clock (ALTCLK) Asynchronous clock (ADACK ADPC5 ADPC4 ADPC3 MC9S08JM60 Series Data Sheet, Rev. 3 Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ ADPC2 ADPC1 ADPC0 Freescale Semiconductor 10-8. ...

Page 147

... AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 10.3.9 Pin Control 2 Register (APCTL2) APCTL2 controls channels 8–15 of the ADC module ADPC15 ADPC14 W Reset Figure 10-11. Pin Control 2 Register (APCTL2) Freescale Semiconductor Description ADPC13 ADPC12 ADPC11 MC9S08JM60 Series Data Sheet, Rev. 3 Analog-to-Digital Converter (S08ADC12V1 ...

Page 148

... AD8 pin I/O control disabled 10.3.10 Pin Control 3 Register (APCTL3) APCTL3 controls channels 16–23 of the ADC module ADPC23 ADPC22 W Reset Figure 10-12. Pin Control 3 Register (APCTL3) 148 Description ADPC21 ADPC20 ADPC19 MC9S08JM60 Series Data Sheet, Rev ADPC18 ADPC17 ADPC16 Freescale Semiconductor ...

Page 149

... The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates with any of the conversion modes and configurations. Freescale Semiconductor Description MC9S08JM60 Series Data Sheet, Rev. 3 ...

Page 150

... The hardware trigger function operates in conjunction with any of the conversion modes and configurations. 10.4.4 Conversion Control Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be 150 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 151

... A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of operation change has occurred and the current conversion is therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Analog-to-Digital Converter (S08ADC12V1) 151 ...

Page 152

... ADCK cycles + 5 bus clock cycles 40 ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 5 μ ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles 40 ADCK cycles Freescale Semiconductor ). ...

Page 153

... ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1). Freescale Semiconductor 23 ADCK Cyc 5 bus Cyc + 8 MHz/1 Number of bus cycles = 3.5 μ ...

Page 154

... ADC module. You can configure the module for 8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 10-8, and Table 10-9 for information used in this example. 154 NOTE Section 10.4.4.2, “Completing MC9S08JM60 Series Data Sheet, Rev. 3 Table 10-7, Freescale Semiconductor ...

Page 155

... Software trigger selected Compare function disabled Not used in this example Reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel MC9S08JM60 Series Data Sheet, Rev ...

Page 156

... The following sections discuss the external pins associated with the ADC module and how they should be used for best results. 156 Reset Initialize ADC ADCCFG = 0x98 ADCSC2 = 0x00 ADCSC1 = 0x41 No Check COCO=1? Yes Read ADCRH Then ADCRL To Clear COCO Bit Continue MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 157

... Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to V Freescale Semiconductor DDAD and V must be connected to the same voltage potential ...

Page 158

... REFH REFL to V DDAD SSAD at a quiet point in the ground plane. SS MC9S08JM60 Series Data Sheet, Rev. 3 and the input is equal to or REFL and V are REFH REFL when the sampling REFL ) is kept high for less than DDAD LEAK . . Freescale Semiconductor ...

Page 159

... This error is defined as the difference between the actual code width of FS the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1 mode). If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its ideal ( used. LSB Freescale Semiconductor ) on the selected input channel lsb = ( ...

Page 160

... Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. 160 reduces this error. MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 161

... The two pins associated with this module, SCL and SDA, are shared with PTC0 and PTC1, respectively. MC9S08JM60 series devices operate at a higher voltage range (2 5.5 V) and do not include stop1 mode. Therefore, please disregard references to stop1. Freescale Semiconductor NOTE MC9S08JM60 Series Data Sheet, Rev. 3 161 ...

Page 162

... SS1 PTE7/SS1 SPSCK1 PTE6/SPSCK1 MOSI1 PTE5/MOSI1 MISO1 PTE4/MISO1 TPMCLK TPM1CH1 PTE3/TPM1CH1 TPM1CH0 PTE2/TPM1CH0 TPM1CHx 4 RxD1 PTE1/RxD1 TxD1 PTE0/TxD1 PTF7 TPMCLK PTF6 TPM2CH1 PTF5/TPM2CH1 TPM2CH0 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 KBIPx 4 PTF1/TPM1CH3 PTF0/TPM1CH2 KBIPx 4 EXTAL PTG5/EXTAL XTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 163

... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. 11.1.3 Block Diagram Figure 11 block diagram of the IIC. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 163 ...

Page 164

... FREQ_REG ADDR_REG STATUS_REG Start Stop Arbitration Control SCL SDA Figure 11-2. IIC Functional Block Diagram memory chapter of this document for the absolute address MC9S08JM60 Series Data Sheet, Rev. 3 Data Bus Interrupt DATA_MUX DATA_REG In/Out Data Shift Register Address Compare Freescale Semiconductor ...

Page 165

... Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA AD7 AD6 W Reset Unimplemented or Reserved Field 7–1 Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module. This field is used on AD[7:1] the 7-bit address scheme and the lower seven bits of the 10-bit address scheme ...

Page 166

... MC9S08JM60 Series Data Sheet, Rev. 3 × SDA hold value × SCL Start hold value × SCL Stop hold value SCL Start SCL Stop 3.000 5.500 4.000 5.250 4.000 5.250 4.250 5.125 4.750 5.125 Freescale Semiconductor Eqn. 11-1 Eqn. 11-2 Eqn. 11-3 Eqn. 11-4 ...

Page 167

... SCL SDA Hold (Start) (hex) Divider Value Value 104 21 17 128 112 17 1B 128 17 1C 144 25 1D 160 25 1E 192 33 1F 240 33 Freescale Semiconductor Table 11-4. IIC Divider and Hold Values SCL Hold ICR (Stop) (hex) Value 118 121 3F MC9S08JM60 Series Data Sheet, Rev. 3 ...

Page 168

... IIC Status Register (IICS TCF IAAS W Reset Unimplemented or Reserved 168 MST TX TXAK Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions Description BUSY 0 ARBL Figure 11-6. IIC Status Register (IICS) MC9S08JM60 Series Data Sheet, Rev RSTA SRW RXAK IICIF Freescale Semiconductor ...

Page 169

... If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received 11.3.5 IIC Data I/O Register (IICD Reset 0 0 Freescale Semiconductor Table 11-6. IICS Field Descriptions Description DATA Figure 11-7. IIC Data I/O Register (IICD) MC9S08JM60 Series Data Sheet, Rev ...

Page 170

... AD[10:8] scheme. This field is only valid when the ADEXT bit is set. 170 Table 11-7. IICD Field Descriptions Description NOTE Figure 11-8. IIC Control Register (IICC2) Table 11-8. IICC2 Field Descriptions Description MC9S08JM60 Series Data Sheet, Rev AD10 AD9 AD8 Freescale Semiconductor ...

Page 171

... As shown in defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. Freescale Semiconductor Figure lsb msb ...

Page 172

... The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 172 11-9. There is one clock pulse on SCL for each data bit, the msb being MC9S08JM60 Series Data Sheet, Rev. 3 Figure 11-9). Freescale Semiconductor ...

Page 173

... The first device to complete its high period pulls the SCL line low again. SCL1 SCL2 SCL Internal Counter Reset Freescale Semiconductor Delay Figure 11-10. IIC Clock Synchronization MC9S08JM60 Series Data Sheet, Rev. 3 Figure 11-10). When all ...

Page 174

... The slave-transmitter remains addressed until it receives a stop condition ( repeated start condition (Sr) followed by a different slave address. 174 Table 11-9). When a 10-bit address follows a start condition, R/W Slave Address 2nd byte AD[8:1] Table MC9S08JM60 Series Data Sheet, Rev. 3 Data A ... Data A/A P 11-10 and including Freescale Semiconductor ...

Page 175

... Complete 1-byte transfer Match of received calling address Arbitration Lost 11.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. Freescale Semiconductor Slave Address Slave Address 2nd byte 1st 7 bits A2 Sr ...

Page 176

... SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing it. 176 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 177

... IICEN IICC1 Module configuration TCF IICS Module status flags IICD Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT Address configuration Freescale Semiconductor Module Initialization (Slave) Module Initialization (Master) Register Model AD[7:1] ICR IICIE MST TX TXAK IAAS ...

Page 178

... Clear ARBL Y N IAAS=1 IAAS Data Transfer Address Transfer See Note 2 See Note 1 Y SRW=1 TX/ (Write) N ACK from Y Receiver ? N Read Data Tx Next from IICD Byte and Store Switch to Set RX Rx Mode Mode Dummy Read Dummy Read from IICD from IICD Freescale Semiconductor RX ...

Page 179

... Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 179 ...

Page 180

... MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 181

... The MCG also controls an external oscillator (XOSC) for the use of a crystal or resonator as the external reference clock. For USB operation on the MC9S08JM60 series, the MCG must be configured for PLL engaged external (PEE) mode in order to achieve a MCGOUT frequency of 48 MHz Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 181 ...

Page 182

... PTB0/MISO2/ADP0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2 PTC1/SDA PTC0/SCL PTD7 PTD6 PTD5 PTD4/ADP11 PTD3/KBIP3/ADP10 PTD2/KBIP2/ACMPO PTD1/ADP9/ACMP– PTD0/ADP8/ACMP+ PTE7/SS1 PTE6/SPSCK1 PTE5/MOSI1 PTE4/MISO1 PTE3/TPM1CH1 PTE2/TPM1CH0 4 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 4 PTF1/TPM1CH3 PTF0/TPM1CH2 4 PTG5/EXTAL PTG4/XTAL PTG3/KBIP7 PTG2/KBIP6 PTG1/KBIP1 PTG0/KBIP0 . DD Freescale Semiconductor ...

Page 183

... Can be selected as the clock source for the MCU • Reference divider is provided • Clock source selected can be divided down • BDC clock (MCGLCLK) is provided as a constant divide the DCO output whether in an FLL or PLL mode. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) 183 ...

Page 184

... DCOOUT 9 DCO TRIM PLLS RDIV_CLK Filter FLL LP VCOOUT Charge Phase VCO Pump Detector Internal VDIV Filter PLL /(4,8,12,...,40) Multi-purpose Clock Generator (MCG) MC9S08JM60 Series Data Sheet, Rev. 3 MCGERCLK MCGIRCLK CLKS BDIV MCGOUT n=0-3 Lock Detector LOLS LOCK MCGFFCLK / 2 MCGLCLK Freescale Semiconductor ...

Page 185

... Bypassed Low Power Internal (BLPI) • Bypassed Low Power External (BLPE) • Stop For details see Section 12.4.1, “Operational 12.2 External Signal Description There are no MCG signals that connect off chip. Freescale Semiconductor Modes.” MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) 185 ...

Page 186

... MCG enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before entering stop 0 Internal reference clock is disabled in stop 186 RDIV Description MC9S08JM60 Series Data Sheet, Rev IREFS IRCLKEN IREFSTEN Freescale Semiconductor ...

Page 187

... External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when EREFSTEN the MCG enters stop mode. 1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or BLPE mode before entering stop 0 External reference clock is disabled in stop Freescale Semiconductor RANGE HGO ...

Page 188

... An additional fine trim bit is available in MCGSC as the FTRIM bit TRIM[7:0] value stored in nonvolatile memory used, it’s the user’s responsibility to copy that value from the nonvolatile memory location to this register. 188 5 4 TRIM Figure 12-5. MCG Trim Register (MCGTRM) Description MC9S08JM60 Series Data Sheet, Rev Freescale Semiconductor ...

Page 189

... CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 — Output of FLL is selected. 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Output of PLL is selected. Freescale Semiconductor 5 4 PLLST IREFST Description ...

Page 190

... PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all PLLS modes. If the PLLS is set, the FLL is disabled in all modes. 1 PLL is selected 0 FLL is selected 190 Description CME 0 0 Figure 12-7. MCG PLL Register (MCGPLL) Description MC9S08JM60 Series Data Sheet, Rev VDIV Freescale Semiconductor 0 1 ...

Page 191

... Encoding 8 — Multiply by 32. 1001 Encoding 9 — Multiply by 36. 1010 Encoding 10 — Multiply by 40. 1011 Encoding 11 — Reserved (default to M=40). 11xx Encoding 12-15 — Reserved (default to M=40). Freescale Semiconductor Description MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) 191 ...

Page 192

... CLKS=10 IREFS=0 PLLS=0 CLKS=10 BDM Enabled BDM Disabled or LP=0 and LP=1 Bypassed Low Power External (BLPE) IREFS=0 CLKS=10 PLLS=1 BDM Enabled or LP=0 IREFS=0 CLKS=00 PLLS=1 Returns to state that was active before MCU entered stop, unless RESET occurs while in stop. Freescale Semiconductor ...

Page 193

... FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUT clock is driven from the external reference clock. The FLL bypassed external mode is entered when all the following conditions occur: Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) ...

Page 194

... VDIV bits, times the reference frequency, as selected by the RDIV bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two. If BDM is not enabled then the FLL is disabled in a low power state. 194 NOTE 12.5.2.4, “Example # 4: Moving MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 195

... The bypassed low power external (BLPE) mode is entered when all the following conditions occur: • CLKS bits are written to 10 • IREFS bit is written to 0 • PLLS bit is written • LP bit is written to 1 • BDM mode is not active Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) 195 ...

Page 196

... For details see Figure 12-8. 12.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 196 MC9S08JM60 Series Data Sheet, Rev. 3 Freescale Semiconductor ...

Page 197

... MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and RDIV values: Freescale Semiconductor chapter). MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) Device Overview chapter) ...

Page 198

... FLL will acquire lock in t Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the MCGSC register, and 0xFFAF for storing the 8-bit trim value in the MCGTRM register. The MCU will not automatically copy the values in these FLASH locations to the respective registers ...

Page 199

... MHz. The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or PLL clock has an appropriate reference clock frequency to switch to. Freescale Semiconductor MC9S08JM60 Series Data Sheet, Rev. 3 Multi-Purpose Clock Generator (S08MCGV1) 199 ...

Page 200

... R must be in the range of ext 31.25 kHz to 39.0625 kHz must be in the range of ext 31.25 kHz to 39.0625 kHz Typical kHz int must be in the range of 1 ext MHz to 2 MHz must be in the range of 1 ext MHz to 2 MHz Freescale Semiconductor ...

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