MC9S12DG128VPVE Freescale, MC9S12DG128VPVE Datasheet

MC9S12DG128VPVE

Manufacturer Part Number
MC9S12DG128VPVE
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S12DG128VPVE

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
50MHz
Interface Type
SCI/SPI/I2C/CAN
Total Internal Ram Size
8KB
# I/os (max)
91
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.25V
Operating Supply Voltage (min)
2.25/2.35/4.5V
On-chip Adc
2(8-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
128KB
Lead Free Status / RoHS Status
Compliant

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MC9S12DG128VPVE
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FREESCALE
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Freescale Semiconductor
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MC9S12DG128VPVE
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MC9S12DT128
Device User Guide
Covers MC9S12DT128E, MC9S12DG128E,
MC9S12DJ128E, MC9S12DG128, MC9S12DJ128,
MC9S12DB128, MC9S12A128, SC515846, SC515847,
SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204,
SC102205
HCS12
Microcontrollers
9S12DT128DGV2/D
V02.16
12 APR 2008
freescale.com

Related parts for MC9S12DG128VPVE

MC9S12DG128VPVE Summary of contents

Page 1

... MC9S12DT128 Device User Guide Covers MC9S12DT128E, MC9S12DG128E, MC9S12DJ128E, MC9S12DG128, MC9S12DJ128, MC9S12DB128, MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG, SC101161DJ, SC102202, SC102203, SC102204, SC102205 HCS12 Microcontrollers 9S12DT128DGV2/D V02.16 12 APR 2008 freescale.com ...

Page 2

... Flash with 2 Bit Backdoor Key Enable Additional CAN0 routing to PJ7,6 Improved BDM with sync and acknowledge capabilities New Part ID number Improvements: Significantly improved NVM reliability data Corrections: Interrupt vector Table Updated Block User Guide versions in preface Updated Appendix A Electrical Characteristics Freescale Semiconductor ...

Page 3

... V02.05 2002 2002 06 Nov 06 Nov V02.06 2002 2002 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Author Description of Changes Changed XCLKS to PE7 in Table 2-2 Updated device part numbers in Figure 2-1 Updated BDM clock in Figure 3-1 Removed SIM description in overview & n Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH ...

Page 4

... Added part numbers SC515846, SC515847, SC515848, and SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2, and section 23. Corrected and added maskset 4L40K in tables 0-1 & 0-2 and section 1.6. Corrected BDLC module availability in DB128 80QFP part in “Derivative Differences” table 0-2. Freescale Semiconductor ...

Page 5

... Oct V02.15 2005 2005 12 Apr 12 Apr V02.16 2008 2008 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Author Description of Changes Added maskset 0L94R Added items V IH,EXTAL “Oscillator characteristics” Removed item “Oscillator” from table A-4 “Operating Conditions” already covered in table “Oscillator Characteristics” ...

Page 6

... Device User Guide — 9S12DT128DGV2/D V02.16 6 Freescale Semiconductor ...

Page 7

... PE3 / LSTRB / TAGLO — Port E I/O Pin 2.3.17 PE2 / R/W — Port E I/O Pin 2.3.18 PE1 / IRQ — Port E Input Pin 2.3.19 PE0 / XIRQ — Port E Input Pin 2.3.20 PH7 / KWH7 — Port H I/O Pin Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 7 ...

Page 8

... PS5 / MOSI0 — Port S I/O Pin 2.3.52 PS4 / MISO0 — Port S I/O Pin 2.3.53 PS3 / TXD1 — Port S I/O Pin 2.3.54 PS2 / RXD1 — Port S I/O Pin 2.3.55 PS1 / TXD0 — Port S I/O Pin 2.3.56 PS0 / RXD0 — Port S I/O Pin Freescale Semiconductor ...

Page 9

... Pseudo Stop 4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.4 Run Section 5 Resets and Interrupts 5.1 Overview 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2.1 Vector Table 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.1 I/O pins 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Section 6 HCS12 Core Block Description 6.1 CPU Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 9 ...

Page 10

... Section 13 Serial Peripheral Interface (SPI) Block Description Section 14 J1850 (BDLC) Block Description Section 15 Byteflight (BF) Block Description 15.1 Device-specific information Section 16 Pulse Width Modulator (PWM) Block Description Section 17 Flash EEPROM 128K Block Description Section 18 EEPROM 2K Block Description Section 19 RAM Block Description 10 Freescale Semiconductor ...

Page 11

... Voltage Regulator 117 A.5 Reset, Oscillator and PLL 119 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 A.6 MSCAN 127 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 11 ...

Page 12

... Device User Guide — 9S12DT128DGV2/D V02.16 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 A.8.1 General Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Appendix B Package Information B.1 General 137 B.2 112-pin LQFP package 138 B.3 80-pin QFP package 139 12 Freescale Semiconductor ...

Page 13

... Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure A-6 SPI Master Timing (CPHA = 129 Figure A-7 SPI Master Timing (CPHA =1 130 Figure A-8 SPI Slave Timing (CPHA = 131 Figure A-9 SPI Slave Timing (CPHA =1 131 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 13 ...

Page 14

... Device User Guide — 9S12DT128DGV2/D V02.16 Figure A-10 General External Bus Timing 134 Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987 138 14 Freescale Semiconductor ...

Page 15

... Flash Control Register (fts128k2) .............................................................. 44 $0110 - $011B EEPROM Control Register (eets2k) .......................................................... 44 $011C - $011F Reserved for RAM Control Register .......................................................... 45 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 45 $0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ................................................ 46 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 15 ...

Page 16

... Table A-12 NVM Reliability Characteristics 114 Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . 117 Table A-14 Startup Characteristics 119 Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table A-18 SPI Master Mode Timing Characteristics 130 16 Freescale Semiconductor ...

Page 17

... Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 17 ...

Page 18

... Device User Guide — 9S12DT128DGV2/D V02.16 18 Freescale Semiconductor ...

Page 19

... Temp Options AEC qualified Yes An errata exists Notes contact Sales Office Table 0-2 Derivative Differences for MC9S12DB128 Modules # of CANs J1850/BDLC Byteflight Package Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table 0-1 Derivative Differences 3 3 MC9S12DG128E MC9S12DJ128E MC9S12DG128 4 4 SC515847 5 5 ...

Page 20

... Sales Office Package Option Temperature Option Device Title Controller Family MC9S12DB128 4 SC515846 6 SC102202 FU 3L40K, 0L94R 4L40K , 5L40K , 2L94R Yes An errata exists Temperature Options C = -40˚C to 85˚ -40˚C to 105˚ -40˚C to 125˚C Package Options FU = 80QFP PV = 112LQFP PVE = lead-free 112LQFP Freescale Semiconductor ...

Page 21

... User Guide), if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)). Pins not available in 80 pin QFP package for MC9S12DG128E, MC9S12DG128, • MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 21 ...

Page 22

... Base+$000C. Therefore care must be taken not to clear this bit. – Port M[1:0] PM1:0 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. – Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input. 22 Freescale Semiconductor ...

Page 23

... Byte Level Data Link Controller -J1850 (BDLC) Block User Guide Motorola Scalable CAN (MSCAN) Block User Guide Voltage Regulator (VREG) Block User Guide Port Integration Module (PIM_9DTB128) Block User Guide Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table 0-3 Document References HCS12 CPU Reference Manual ...

Page 24

... Device User Guide — 9S12DT128DGV2/D V02.16 24 Freescale Semiconductor ...

Page 25

... CRG (Clock and Reset Generator) – Choice of low current Colpitts oscillator or standard Pierce Oscillator – PLL – COP watchdog – real time interrupt – clock monitor • 8-bit and 4-bit ports with interrupt functionality Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 25 ...

Page 26

... Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input – Usable as interrupt inputs • Serial interfaces – Two asynchronous Serial Communications Interfaces (SCI) – Two Synchronous Serial Peripheral Interface (SPI) – Byteflight • Byte Data Link Controller (BDLC) 26 Freescale Semiconductor ...

Page 27

... Emulation Expanded Wide Mode – Emulation Expanded Narrow Mode • Special Operating Modes – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Freescale use only) – Special Peripheral Mode (Freescale use only) Low power modes • Stop Mode • ...

Page 28

... Device User Guide — 9S12DT128DGV2/D V02.16 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT128 device. 28 Freescale Semiconductor ...

Page 29

... Internal Logic 2.5V I/O Driver 5V V DD1,2 V SS1,2 A/D Converter 5V & PLL 2.5V Voltage Regulator Reference V DDPLL V SSPLL Voltage Regulator 5V & I/O Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 VRH ATD0 VRL VDDA VSSA AN0 AN1 AN2 AN3 AN4 AN5 AN6 ...

Page 30

... Flash EEPROM Page Window 30 $07FF) is hidden by the register space ($0000 - $03FF) and the RAM – Table 1-1 Device Memory Map Module Fixed Flash EEPROM array incl. 0.5K, 1K Protected Sector at start Size (Bytes 160 2048 8192 16384 16384 Freescale Semiconductor ...

Page 31

... The address does not show the map after reset, but a useful map. After reset the map is: $0000 – $03FF: Register Space $0000 – $1FFF: 8K RAM $0000 – $07FF: 2K EEPROM (not visible) Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table 1-1 Device Memory Map Module Fixed Flash EEPROM array incl ...

Page 32

... EE13 EE12 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit Bit 1 Bit Bit LSTRE RDWE 0 IVIS EMK EME 0 0 PUPBE PUPAE 0 0 RDPB RDPA ESTR Bit 3 Bit 2 Bit 1 Bit RAM11 RAMHAL REG11 0 0 EE11 EEON EXSTR1 EXSTR0 ROMHM ROMON Freescale Semiconductor ...

Page 33

... Read: reg_sw0 $001C MEMSIZ0 Write: Read: rom_sw1 rom_sw0 $001D MEMSIZ1 Write: $001E - $001E Address Name Read: $001E INTCR Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 INT map (HCS12 Interrupt) Bit 7 Bit 6 Bit 5 Bit WRINT INTE INTC INTA INT8 MMC map (HCS12 Module Mapping Control) ...

Page 34

... Bit 0 0 PSEL3 PSEL2 PSEL1 Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit BK0V3 BK0V2 BK0V1 BK0V0 Bit Bit 0 BK1V3 BK1V2 BK1V1 BK1V0 Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 PIX3 PIX2 PIX1 PIX0 Bit 3 Bit 2 Bit 1 Bit Bit Bit 0 Freescale Semiconductor ...

Page 35

... Write: Read: $0045 TCNT (lo) Write: Read: $0046 TSCR1 Write: Read: $0047 TTOV Write: Read: $0048 TCTL1 Write: Read: $0049 TCTL2 Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 CRG (Clock and Reset Generator) Bit 7 Bit 6 Bit 5 Bit SYN5 SYN4 RTIF ...

Page 36

... EDG1A EDG0B EDG0A C3I C2I C1I C0I TCRE PR2 PR1 PR0 C3F C2F C1F C0F Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0 CLK1 CLK0 PAOVI PAI 0 0 PAOVF PAIF Bit 0 Freescale Semiconductor ...

Page 37

... Read: $0077 MCCNT (lo) Write: Read: $0078 TC0H (hi) Write: Read: $0079 TC0H (lo) Write: Read: $007A TC1H (hi) Write: Read: $007B TC1H (lo) Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 ECT (Enhanced Capture Timer 16 Bit 8 Channels) Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit ...

Page 38

... Bit7 Bit15 Bit7 Bit6 0 0 Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit 0 Bit 3 Bit 2 Bit 1 Bit ASCIF ETRIG ASCIE S1C FIFO FRZ1 FRZ0 PRS3 PRS2 PRS1 PRS0 CC2 CC1 CC0 CCF3 CCF2 CCF1 CCF0 Bit BIT Bit8 Freescale Semiconductor ...

Page 39

... PWMCTL Write: Read: PWMTST $00A6 Test Only Write: Read: PWMPRSC $00A7 Test Only Write: Read: $00A8 PWMSCLA Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Bit 6 Bit 5 Bit 4 Bit15 Bit7 Bit6 0 0 Bit15 ...

Page 40

... Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 3 Bit 2 Bit 1 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 0 Freescale Semiconductor ...

Page 41

... SCI1BDH Write: Read: $00D1 SCI1BDL Write: Read: $00D2 SCI1CR1 Write: Read: $00D3 SCI1CR2 Write: Read: $00D4 SCI1SR1 Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit PWMIF PWMIE PWMLVL ...

Page 42

... Bit 2 Bit 1 Bit 0 0 RAF BRK13 TXDIR Bit 3 Bit 2 Bit 1 Bit 0 CPOL CPHA SSOE LSBFE 0 SPISWAI SPC0 0 SPR2 SPR1 SPR0 Bit0 Bit 3 Bit 2 Bit 1 Bit 0 ADR3 ADR2 ADR1 0 IBC3 IBC2 IBC1 IBC0 0 0 TXAK IBSWAI RSTA 0 SRW RXAK IBIF Freescale Semiconductor ...

Page 43

... Write: Read: $00F6 Reserved Write: Read: $00F7 Reserved Write: $00F8 - $00FF Address Name Read: $00F8 - Reserved $00FF Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 BDLC (Byte Level Data Link Controller J1850) Bit 7 Bit 6 Bit 5 Bit IMSG CLKS SMRST DLOOP ...

Page 44

... FDIV2 FDIV1 FDIV0 NV3 NV2 SEC1 SEC0 BKSEL1 BKSEL0 FPHS0 FPLDIS FPLS1 FPLS0 BLANK 0 0 CMDB2 CMDB0 Bit Bit Bit Bit Bit 3 Bit 2 Bit 1 Bit 0 EDIV3 EDIV2 EDIV1 EDIV0 EPDIS EP2 EP1 EP0 BLANK 0 0 CMDB2 CMDB0 Bit 9 Bit 8 Freescale Semiconductor ...

Page 45

... ATD1STAT1 Write: Read: $012C Reserved Write: Read: $012D ATD1DIEN Write: Read: $012E Reserved Write: Read: $012F PORTAD1 Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 EEPROM Control Register (eets2k) Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Reserved for RAM Control Register ...

Page 46

... WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 Bit 3 Bit 2 Bit 1 Bit Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit8 Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ 0 SLPAK INITAK WUPM BRP3 BRP2 BRP1 BRP0 TSTAT1 TSTAT0 OVRIF RXF OVRIE RXFIE Freescale Semiconductor ...

Page 47

... Standard ID Read: CANxRIDR1 Write: Extended ID Read: $xxx2 Standard ID Read: CANxRIDR2 Write: Extended ID Read: $xxx3 Standard ID Read: CANxRIDR3 Write: Read: $xxx4- CANxRDSR0 - $xxxB CANxRDSR7 Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 CAN0 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit ...

Page 48

... DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 PRIO3 PRIO2 PRIO1 PRIO0 TSR11 TSR10 TSR9 TSR8 TSR3 TSR2 TSR1 TSR0 Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ 0 SLPAK INITAK WUPM BRP3 BRP2 BRP1 BRP0 TSTAT1 TSTAT0 OVRIF RXF Freescale Semiconductor ...

Page 49

... Address Name Read: $01C0 - Reserved $01FF Write: $0200 - $023F Address Name Read: $020C - Reserved $023F Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 CAN1 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 ...

Page 50

... RDRS2 RDRS1 RDRS0 PERS3 PERS2 PERS1 PERS0 PPSS3 PPSS2 PPSS1 PPSS0 PTM3 PTM2 PTM1 PTM0 PTIM3 PTIM2 PTIM1 PTIM0 DDRM3 DDRM2 DDRM1 DDRM0 RDRM3 RDRM2 RDRM1 RDRM0 PERM3 PERM2 PERM1 PERM0 PPSM3 PPSM2 PPSM1 PPSM0 PTP3 PTP2 PTP1 PTP0 Freescale Semiconductor ...

Page 51

... PPSJ Write: Read: $026E PIEJ Write: Read: $026F PIFJ Write: Read: $0270 - Reserved $027F Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 PIM (Port Integration Module) Bit 7 Bit 6 Bit 5 Bit 4 PTIP7 PTIP6 PTIP5 PTIP4 DDRP7 DDRP7 DDRP5 DDRP4 RDRP7 ...

Page 52

... TSTAT0 OVRIF RXF OVRIE RXFIE 0 TXE2 TXE1 TXE0 0 TXEIE2 TXEIE1 TXEIE0 0 ABTRQ2 ABTRQ1 ABTRQ0 0 ABTAK2 ABTAK1 ABTAK0 0 TX2 TX1 TX0 0 IDHIT2 IDHIT1 IDHIT0 AC3 AC2 AC1 AC0 AM3 AM2 AM1 AM0 AC3 AC2 AC1 AC0 AM3 AM2 AM1 AM0 Freescale Semiconductor ...

Page 53

... BFPCTLBF Write: Read: $0311 Reserved Write: Read: $0312 BFBUFLOCK Write: Read: $0313 Reserved Write: Read: $0314 BFFIDRJ Write: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Reserved Bit 7 Bit 6 Bit 5 Bit Byteflight Bit 7 Bit 6 Bit 5 Bit 4 SLPAK INITRQ MASTER ALARM ...

Page 54

... ID3 ID2 ID1 ID0 LEN3 LEN2 LEN1 LEN0 DATA3 DATA2 DATA1 DATA0 ID3 ID2 ID1 ID0 LEN3 LEN2 LEN1 LEN0 DATA3 DATA2 DATA1 DATA 0 ID3 ID2 ID1 ID0 LEN3 LEN2 LEN1 LEN0 DATA3 DATA2 DATA1 DATA0 0 0 ABTRQ CFG Freescale Semiconductor ...

Page 55

... The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Reserved ...

Page 56

... Device User Guide — 9S12DT128DGV2/D V02.16 56 Freescale Semiconductor ...

Page 57

... The MC9S12DT128 and its derivatives are available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1, Figure 2-2, and Figure 2-3 show the pin assignments for different packages. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 57 ...

Page 58

... MC9S12DB128, MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG, SC101161DJ, SC102202, SC102203, SC102204, SC102205 112LQFP 84 VRH 83 VDDA 82 PAD15/AN15/ETRIG1 81 PAD07/AN07/ETRIG0 80 PAD14/AN14 79 PAD06/AN06 78 PAD13/AN13 77 PAD05/AN05 76 PAD12/AN12 75 PAD04/AN04 74 PAD11/AN11 73 PAD03/AN03 72 PAD10/AN10 71 PAD02/AN02 70 PAD09/AN09 69 PAD01/AN01 68 PAD08/AN08 67 PAD00/AN00 66 VSS2 65 VDD2 64 PA7/ADDR15/DATA15 63 PA6/ADDR14/DATA14 62 PA5/ADDR13/DATA13 61 PA4/ADDR12/DATA12 60 PA3/ADDR11/DATA11 59 PA2/ADDR10/DATA10 58 PA1/ADDR9/DATA9 57 PA0/ADDR8/DATA8 Freescale Semiconductor ...

Page 59

... ADDR3/DATA3/PB3 19 ADDR4/DATA4/PB4 20 Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Bondout Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, SC102204 ...

Page 60

... SC101161DG, SC101161DJ, SC102203, and SC102204 80-pin package options. Signals shown in Italics are not available on MC9S12DB128, SC515846, and SC102202 80-pin package options MC9S12DB128, SC515846, 50 SC102202 49 80 QFP Bondout VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 Freescale Semiconductor ...

Page 61

... PE3 LSTRB TAGLO PE2 R/W — PE1 IRQ — PE0 XIRQ — PH7 KWH7 --- Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table 2-1 Signal Properties Pin Name Pin Name Powered Function 4 Function 5 by — — VDDPLL — — VDDPLL — ...

Page 62

... Disabled PPSM TX of CAN0, CAN4, SCK of SPI0 Port M I/O, BF sync pulse (Rx/Tx) OK PERM/ Disabled pulse o/ PPSM CAN0, CAN4, MOSI of SPI0 Port M I/ BF, PERM/ Disabled CAN1, CAN0 PPSM SPI0 Port M I/ BF, PERM/ Disabled CAN1, CAN0, MISO PPSM of SPI0 Freescale Semiconductor ...

Page 63

... PS1 TXD0 — PS0 RXD0 — PT[7:0] IOC[7:0] — NOTES: 1. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Pin Name Pin Name Powered Function 4 Function 5 by — — VDDX — ...

Page 64

... The TEST pin must be tied to VSS in all applications. 2.3.4 XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. Figure 2-4 PLL Loop Filter Connections 2.3.5 BKGD / TAGHI / MODC — ...

Page 65

... If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 65 ...

Page 66

... Refer to manufacturer’s data. Figure 2-6 Pierce Oscillator Connections (PE7=0) MCU Figure 2-7 External Clock Connections (PE7=0) 66 EXTAL XTAL EXTAL R B ceramic resonator * R S XTAL EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) XTAL not connected Crystal or ceramic resonator VSSPLL . C 1 Crystal VSSPLL Freescale Semiconductor ...

Page 67

... This will wake up the MCU from STOP or WAIT mode. 2.3.20 PH7 / KWH7 — Port H I/O Pin 7 PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 67 ...

Page 68

... PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller (CAN0, CAN4) or the serial clock pin SCL of the IIC module. 68 Freescale Semiconductor ...

Page 69

... PM5 is a general purpose input or output pin. It can be configured as the reception OK output pulse pin of Byteflight. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 69 ...

Page 70

... STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. 2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6 PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. 70 Freescale Semiconductor ...

Page 71

... PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0). 2.3.50 PS6 / SCK0 — Port S I/O Pin 6 PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 71 ...

Page 72

... Power Supply Pins MC9S12DT128 power and ground pins are described below. Table 2-2 MC9S12DT128 Power and Ground Connection Summary Pin Number Mnemonic 112-pin QFP VDD1, 2 13, 65 VSS1 Nominal Voltage 2.5V Internal power and ground generated by internal regulator 0V Description Freescale Semiconductor ...

Page 73

... MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE: No load allowed except for bypass capacitors. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Nominal Voltage 5.0V External power and ground, supply to pin drivers and internal voltage regulator ...

Page 74

... Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator. NOTE: No load allowed except for bypass capacitors. 2.4.7 VREGEN — On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally. 74 Freescale Semiconductor ...

Page 75

... Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. EXTAL CRG XTAL Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 core clock bus clock oscillator clock Figure 3-1 Clock Connections ...

Page 76

... Device User Guide — 9S12DT128DGV2/D V02.16 76 Freescale Semiconductor ...

Page 77

... For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide. Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS 1 0 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table 4-1 Mode Selection PK7 = ROMON ROMCTL Bit Special Single Chip, BDM allowed and ACTIVE. BDM is ...

Page 78

... The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. 78 Description Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V Freescale Semiconductor ...

Page 79

... The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks. 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 79 ...

Page 80

... Device User Guide — 9S12DT128DGV2/D V02.16 80 Freescale Semiconductor ...

Page 81

... Pulse accumulator A overflow $FFDA, $FFDB Pulse accumulator input edge $FFD8, $FFD9 $FFD6, $FFD7 $FFD4, $FFD5 $FFD2, $FFD3 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 CCR Mask Reset None None COPCTL (CME, FCME) None None ...

Page 82

... BFRIER (RCVFIE) BFBUFCTL[15:0] (IENA) BFRIER (SYNAIE, SYNNIE) BFBUFCTL[15:0] (IENA), BFGIER (OVRNIE, ERRIE, SYNEIE, SYNLIE, ILLPIE, LOCKIE, WAKEIE) BFRIER (SLMMIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) PIEP (PIEP7-0) PWMSDN (PWMIE) $8C Freescale Semiconductor $B8 $B6 $B4 $B2 $B0 $A8 $A6 $A4 $A2 $A0 $96 $94 $92 $90 ...

Page 83

... Refer to Table 2-1 for affected pins. 5.3.2 Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 83 ...

Page 84

... Device User Guide — 9S12DT128DGV2/D V02.16 84 Freescale Semiconductor ...

Page 85

... Reset state: $80 6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module. 6.3.1 Device-specific information • PUCR – Reset state: $90 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 85 ...

Page 86

... Section 8 Oscillator (OSC) Block Description Consult the OSC Block User Guide for information about the Oscillator module. 8.1 Device-specific information The XCLKS input signal is active low (see 2.3. NOACC / XCLKS Section 9 Enhanced Capture Timer (ECT) Block Description 86 — Port E I/O Pin 7). Freescale Semiconductor ...

Page 87

... Section 14 J1850 (BDLC) Block Description Consult the BDLC Block User Guide for information about the J1850 module. Section 15 Byteflight (BF) Block Description Consult the BF Block User Guide for information about the 10 Mbps Byteflight module. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 87 ...

Page 88

... Section 21 Port Integration Module (PIM) Block Description Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module. Section 22 Voltage Regulator (VREG) Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator. 88 Freescale Semiconductor ...

Page 89

... Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. • Central power input should be fed in at the VDDA/VSSA pins. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Purpose Type VDD1 filter cap ceramic X7R VDD2 fi ...

Page 90

... Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VDD1 C1 VSS1 90 VSSA VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 Freescale Semiconductor ...

Page 91

... Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Colpitts Oscillator VDD1 C1 VSS1 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 VSSA VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 ...

Page 92

... Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VDD1 C1 VSS1 92 VSSX VSSR R3 VDDR R2 Q1 VDDPLL R1 VSSA C3 VDDA VSS2 C2 VDD2 VSSPLL Freescale Semiconductor ...

Page 93

... Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Pierce Oscillator VDD1 C1 VSS1 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 VSSA VSSX VSSR R3 VDDR R2 Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 ...

Page 94

... Device User Guide — 9S12DT128DGV2/D V02.16 Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and VDD1 C1 VSS1 94 SC102202) Pierce Oscillator VSSA VSSX VSSR R3 VDDR R2 Q1 VSSPLL VDDPLL R1 C3 VDDA VSS2 C2 VDD2 VSSPLL Freescale Semiconductor ...

Page 95

... Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 95 ...

Page 96

... Device User Guide — 9S12DT128DGV2/D V02.16 96 Freescale Semiconductor ...

Page 97

... VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 97 ...

Page 98

... Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e. system clock is present clock rate is very low which would reduce overall power consumption range during instantaneous and DD5 DD > greater than I in DD5 Freescale Semiconductor , the DD5 ...

Page 99

... All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Rating ...

Page 100

... LAT I LAT and the junction temperature T A Symbol Value Unit R1 1500 Ohm C 100 pF – – Ohm C 200 pF – – –2.5 V 7.5 V Min Max Unit 2000 – 200 – MM 500 – +100 – –100 +200 – –200 . For power dissipation J Freescale Semiconductor ...

Page 101

... Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (T obtained from Junction Temperature Ambient Temperature Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table A-4 Operating Conditions Symbol Min V DD5 V 2.35 ...

Page 102

... Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. 102 INT + DDPLL V DDPLL DSON ----------- - for outputs driven low ; DD5 V OH – = ----------------------------------- - for outputs driven high ; DDR V DDR I DDA V DDA + DSON DDA V DDA Freescale Semiconductor ...

Page 103

... PC Board according to EIA/JEDEC Standard 51-7 A.1.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 1 Symbol Min ...

Page 104

... DD5 0.35*V – – DD5 V – 0.3 – – SS5 250 -1.0 – 1.0 V – 0.8 – – DD5 – – 0.8 – – –130 –10 – – – – 130 10 – – 6 – –2.5 – 2.5 – Freescale Semiconductor Unit ...

Page 105

... Pseudo Stop Current (RTI and COP enabled (2) Stop Current Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Symbol I DD5 I DDW (1) only RTI enabled DDPS “C” Temp Option 100 C 105 C “V” Temp Option 120 C 125 C “M” Temp Option 140 C ...

Page 106

... Device User Guide — 9S12DT128DGV2/D V02.16 NOTES: 1. PLL off, Oscillator in Colpitts Mode 2. At those low power dissipation levels T 106 = T can be assumed J A Freescale Semiconductor ...

Page 107

... Due to the input pin leakage current as specified in (Table A-6) in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 This constraint exists since the sample buffer amplifier can not drive ...

Page 108

... C Disruptive Analog Input Current 4 C Coupling Ratio positive current injection 5 C Coupling Ratio negative current injection 108 1024 * (C – INS INN and $000 for values less than RH Symbol Min Typ INN C INS I -2 Freescale Semiconductor = ERR S Max Unit 2 A A/A 10 ...

Page 109

... These values include the quantization error which is inherently 1/2 count for any A/D converter. For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. The Integral Non-Linearity (INL) is defined as the sum of all DNLs: INL n Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Symbol Min LSB ...

Page 110

... Figure A-1 shows only definitions, for specification values refer to Table A-10. 110 10-Bit Absolute Error Boundary V i 8-Bit Absolute Error Boundary Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 5055 5060 5065 5070 5075 5080 $FF $FE $ 5085 5090 5095 5100 5105 5110 5115 5120 Freescale Semiconductor Vin mV ...

Page 111

... The time to program a consecutive word can be calculated as: The time to program a whole row is: Row programming is more than 2 times faster than single word programming. A.3.1.3 Sector Erase Erasing a 512 byte Flash sector byte EEPROM sector takes: Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02. ...

Page 112

... Typ Max 0 150 200 2 46 74.5 (2) 20.4 31 (2) 678.4 1035 26.7 (5) 100 133 6 11 32778 (6) 11 1034 and maximum bus frequency NVMOP and bus frequency f NVMOP . NVMOP Freescale Semiconductor Unit 1 MHz MHz kHz 3 s (3) s (3) s ( cyc (7) t cyc . bus ...

Page 113

... The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 113 ...

Page 114

... Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. 3. Spec table quotes typical endurance evaluated for this product family, typical endurance at various temperature can be estimated using the graph below ...

Page 115

... Figure A-2 Typical Endurance vs Temperature 500 450 400 350 300 250 200 150 100 50 0 -40 -20 ------ Flash ------ EEPROM Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02. Operating Temperature T J 120 100 140 [ C] 115 ...

Page 116

... Device User Guide — 9S12DT128DGV2/D V02.16 116 Freescale Semiconductor ...

Page 117

... The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Symbol Min Typ C 220 ...

Page 118

... Device User Guide — 9S12DT128DGV2/D V02.16 118 Freescale Semiconductor ...

Page 119

... CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. A.5.1.4 Stop Recovery Out of STOP the controller can be woken external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table A-14 Startup Characteristics Symbol V ...

Page 120

... POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time t 120 specifies the maximum time before switching to the CQOUT . The device also features a clock monitor. A UPOSC the CPU starts wrs Freescale Semiconductor ...

Page 121

... The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Symbol f ...

Page 122

... Phase f 1 ref K Detector f cmp Loop Divider 1 synr+1 = 50MHz and f VCO ref f – vco 60 50 – ---------------------- - ----------------------- - K 1V 100 – 100 e – – = 316.7Hz ref f < ----- - XFC Pin VCO 1MHz. E.g., these frequencies are used = -90.48MHz/V f ref ------------- - 0 < 25kHz Freescale Semiconductor f vco ...

Page 123

... Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 f ...

Page 124

... J N For N < 100, the following equation is a good fit for the maximum jitter: J(N) 1 Figure A-5 Maximum bus clock jitter approximation 124 minN t maxN Figure A-4 Jitter Definitions t N max = max 1 – -------------------- - N t nom ------- - + N min – -------------------- - N t nom N Freescale Semiconductor ...

Page 125

... D Charge pump current tracking mode ( Jitter fit parameter 1 ( Jitter fit parameter 2 NOTES deviation from target frequency 4MHz 25MHz equivalent f OSC BUS 10K . Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Table A-16 PLL Characteristics Symbol f SCM f VCO | trk | Lock | unl | unt ...

Page 126

... Device User Guide — 9S12DT128DGV2/D V02.16 126 Freescale Semiconductor ...

Page 127

... A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C Rating 1 P MSCAN Wake-up dominant pulse filtered 2 P MSCAN Wake-up dominant pulse pass Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 Symbol Min Typ t WUP t 5 ...

Page 128

... Device User Guide — 9S12DT128DGV2/D V02.16 128 Freescale Semiconductor ...

Page 129

... MISO 2 MSB IN (INPUT) 9 MOSI MSB OUT (OUTPUT) 1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6 SPI Master Timing (CPHA = 0) Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02. BIT LSB BIT LSB OUT 129 ...

Page 130

... Master and the Slave timing shown in (Table A-19). 130 BIT BIT 200pF on all outputs LOAD Symbol sck t lead t lag t wsck LSB IN MASTER LSB OUT PORT DATA 1 Min Typ Max 2048 1 2 — 1024 t bus bus Freescale Semiconductor Unit f bus t bus t sck t sck ...

Page 131

... Figure A-8 SPI Slave Timing (CPHA = 0) SS (INPUT) 2 SCK (CPOL 0) (INPUT) 4 SCK (CPOL 1) (INPUT) 9 MISO SLAVE (OUTPUT MOSI MSB IN (INPUT) Figure A-9 SPI Slave Timing (CPHA =1) Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02. BIT BIT BIT MSB OUT 6 BIT ...

Page 132

... D Data Valid (after SCK Edge Data Hold Time (Outputs Rise Time Inputs and Outputs 12 D Fall Time Inputs and Outputs 132 Symbol Min Typ sck t 1 lead t 1 lag wsck cyc dis Freescale Semiconductor Max Unit bus t 2048 bus t cyc t cyc cyc t 1 cyc ...

Page 133

... A.8.1 General Multiplexed Bus Timing The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 133 ...

Page 134

... Device User Guide — 9S12DT128DGV2/D V02.16 ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 PIPO0 PIPO1, PE6,5 Figure A-10 General External Bus Timing 134 addr 7 12 addr data data Freescale Semiconductor ...

Page 135

... D Read/write hold time 27 D Low strobe delay time D Low strobe valid time to E rise ( Low strobe hold time 30 D NOACC strobe delay time D NOACC valid time to E rise (PW 31 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 = 50pF LOAD Symbol cyc PW EL ...

Page 136

... D IPIPO[1:0] valid time to E rise ( IPIPO[1:0] delay time ( IPIPO[1:0] valid time to E fall NOTES: 1. Affected by clock stretch: add 136 = 50pF LOAD Symbol t NOH t P0D – P0D P0V P1D EH P1V t P1V where N=0,1 depending on the number of clock stretches. cyc Min Typ Max Freescale Semiconductor Unit ...

Page 137

... Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DT128 packages. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 137 ...

Page 138

... BSC C --- 1.600 C1 0.050 0.150 C2 1.350 1.450 D 0.270 0.370 E 0.450 0.750 F 0.270 0.330 G 0.650 BSC J 0.090 0.170 K 0.500 REF P 0.325 BSC R1 0.100 0.200 R2 0.100 0.200 S 22.000 BSC S1 11.000 BSC V 22.000 BSC V1 11.000 BSC Y 0.250 REF Z 1.000 REF AA 0.090 0.160 Freescale Semiconductor ...

Page 139

... B.3 80-pin QFP package 0.20 M 0.05 A-B 0. -C- H SEATING PLANE G DATUM -H- PLANE W X DETAIL C Figure 1 80-pin QFP Mechanical Dimensions (case no. 841B) Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02. -B- B DETAIL - A A DETAIL C -H- M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

Page 140

... Device User Guide — 9S12DT128DGV2/D V02.16 140 Freescale Semiconductor ...

Page 141

... User Guide End Sheet Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.16 141 ...

Page 142

... All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components ...

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