EE80C186XL20 S F12 Intel, EE80C186XL20 S F12 Datasheet - Page 13

• Manufacturer Part Number: EE80C186XL20 S F12
• Manufacturer: Intel

Specifications of EE80C186XL20 S F12

• Family Name: Intel186
• Device Core: 80186
• Device Core Size: 16b
• Frequency (max): 20MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Compliant

NOTE
Pin names in parentheses apply to the 80C188XL
SRDY
LOCK
S0
S1
S2
HOLD
HLDA
Name
Pin
Type
Pin
O
O
O
I
I
Input
Type
S(L)
A(L)
Output
States
H(Z)
R(Z)
H(Z)
R(1)
H(1)
R(0)
Table 3 Pin Descriptions (Continued)
Synchronous Ready informs the processor that the addressed
memory space or I O device will complete a data transfer The
SRDY pin accepts an active-HIGH input synchronized to CLKOUT
The use of SRDY allows a relaxed system timing over ARDY This
is accomplished by elimination of the one-half clock cycle required
to internally synchonize the ARDY input signal Connecting SRDY
high will always assert the ready condition to the CPU If this line is
unused it should be tied LOW to yield control to the ARDY pin
LOCK output indicates that other system bus masters are not to
gain control of the system bus LOCK is active LOW The LOCK
signal is requested by the LOCK prefix instruction and is activated
at the beginning of the first data cycle associated with the
instruction immediately following the LOCK prefix It remains active
until the completion of that instruction No instruction prefetching
will occur while LOCK is asserted
Bus cycle status S0 – S2 are encoded to provide bus-transaction
information
S2
S2 may be used as a logical M IO indicator and S1 as a DT R
indicator
HOLD indicates that another bus master is requesting the local bus
The HOLD input is active HIGH The processor generates HLDA
(HIGH) in response to a HOLD request Simultaneous with the
issuance of HLDA the processor will float the local bus and control
lines After HOLD is detected as being LOW the processor will
lower HLDA When the processor needs to run another bus cycle it
will again drive the local bus and control lines
In Enhanced Mode HLDA will go low when a DRAM refresh cycle
is pending in the processor and an external bus master has control
of the bus It will be up to the external master to relinquish the bus
by lowering HOLD so that the processor may execute the refresh
cycle
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Bus Cycle Status Information
Interrupt Acknowledge
Read I O
Write I O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
Bus Cycle Initiated
Pin Description
80C186XL 80C188XL
13