IDT7210L20J IDT, Integrated Device Technology Inc, IDT7210L20J Datasheet - Page 3

• Manufacturer Part Number: IDT7210L20J
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7210L20J

• Package Type: LCC
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Supplier Unconfirmed

IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
PIN DESCRIPTIONS
X
Y
P
P
CLKX
CLKY
CLKP
TSX
TSM
TSL
PREL
ACC
SUB
TC
RND
0
0 - 15
16
32
Pin Name
-
-
-
15
31
34
/ P
0
-
15
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
Designator
Pin 1
Data Inputs
Multiplexed I/O port. Y
are LSP register outputs - enabled by TSL.
MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.
XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when
PREL = 1.
Input data X
Input data Y
Output data loaded into output register on rising edge of CLKP.
TSX = 0 enables XTP outputs, TSX = 1 tristates P
TSM = 0 enables MSP outputs, TSM = 1 tristates P
TSL = 0 enables LSP outputs, TSL = 1 tristates P
When PREL= 1 data is input on P
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a
subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a
simple multipler with no accumulation
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted
from the result and stored back in the output register. When SUB = 0 the contents of the output register
are added to the result and stored back in the output register
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y
inputs are assumed to be in unsigned magnitude form
This input is loaded into the control register on the rising edge of (CLKX + CLKY).
RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and
XTP data
11
10
09
08
07
06
05
04
03
02
01
X
X
Y
NC
X
X
X
X
X
P
A
13
11
0,
9
7
5
3
1
0
0
0 - 15
-
X
X
NC
X
Y
X
X
X
X
X
P
Y
15
P
B
12
10
14
1,
8
6
4
2
0
1
2,
2
loaded in Y input register on CLKY rising edge.
loaded in X input register on CLKX rising edge.
TSL
X
Y
Y
P
P
C
15
3,
4,
3
4
0 - 15
SUB
RND
Y
Y
P
P
D
are data inputs and can be used to preload LSP register on PREL = 1. P
5,
6,
5
6
CLK
GND
ACC
Y
P
TOP VIEW
0
E
7,
7
-
X
15
11.2
PGA
G68-2
CLK
V
Y
Y
P
P
lines. When PREL = 0, inputs on these lines are ignored.
F
CC
8,
9,
8
9
Y
Y
Y
TSX
P
P
TC PREL CLK
G
10,
11,
10
11
Description
0
32
-
TSM
Y
Y
P
P
16
15
12,
13,
H
12
13
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-
-
34
lines.
31
Y
Y
P
P
lines.
P
14,
15,
lines.
14
15
J
34
P
P
P
P
P
P
P
P
P
P
P
NC
K
30
28
26
24
22
20
18
16
33
32
2577 drw 05
P
P
P
P
P
P
P
P
NC
L
31
29
27
25
23
21
19
17
2577 tbl 01
0
-
3
15