MT48H32M16LFCJ-8:A Micron Technology Inc, MT48H32M16LFCJ-8:A Datasheet
MT48H32M16LFCJ-8:A
Specifications of MT48H32M16LFCJ-8:A
Related parts for MT48H32M16LFCJ-8:A
MT48H32M16LFCJ-8:A Summary of contents
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... PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Options • V • Row size option • Configuration • Plastic “green” packages • Timing – cycle time • Power • Operating temperature range ...
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... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Timing Diagrams .53 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2005 Micron Technology, Inc. All rights reserved. ...
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... List of Figures Figure 1: 512Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 2: 32 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 3: 16 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4: 54-Ball FBGA (Top View) – 10mm x 11.5mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 5: 90-Ball VFBGA (Top View) – 10mm x 13mm Figure 6: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 8: EMR Definition ...
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... Specifications and Conditions (x16 and x32 .50 DD Table 16: Capacitance (x16 .51 Table 17: Capacitance (x32 .51 PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2005 Micron Technology, Inc. All rights reserved. ...
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... A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL locations with a read burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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... The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address ...
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... CAS# RAS# EXT MODE REGISTER REFRESH MODE REGISTER COUNTER 13 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM BANK1 13 BANK0 ROW- 13 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 8,192 LATCH ARRAY AND ...
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... Ball Assignments Figure 4: 54-Ball FBGA (Top View) – 10mm x 11.5mm Notes: 1. The E2 pin is a test pin and must be tied to V PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM DQ15 DQ14 DQ13 DD DQ12 DQ11 DQ10 DQ9 DD 1 DQ8 ...
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... Figure 5: 90-Ball VFBGA (Top View) – 10mm x 13mm Notes: 1. The K2 “DNU” ball should not be used in the application. However, it may be connected PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM DQ26 DQ24 V SS DQ28 DQ27 DQ25 DQ29 ...
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... Meg x 16, 16 Meg x 32 Mobile SDRAM Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...
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... A7, F9, L7, R7 A1, E3, J1 A3, F1, L3, R3 – E3, E7 – K2 – PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Symbol Type DQ0–DQ31 I/O Data input/output: Data bus Supply DQ power: Provide isolated power to DQ for improved noise DD immunity. ...
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... Functional Description In general, the 512Mb SDRAMs (4 Meg banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...
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... MRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with the BL being program- mable, as shown in Figure 6 on page 14. The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command continuous locations are available for both the sequential and the interleaved burst types, and a continuous-page burst is available for the sequential type ...
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... Extended mode register 1 1 Reserved M9 Write Burst Mode Programmed burst length 0 1 Single location access – Notes: 1. Should be programmed to “0” to ensure compatibility with future devices. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM A11 A10 M11 M10 ...
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... When the BL programmed via M0–M2 applies to both READ and WRITE bursts; when the programmed BL applies to READ bursts, but write accesses are single- location accesses. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Starting Column Address Type = Sequential A0 0 ...
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... Each READ command may be to any bank. DQM is LOW. 2. For DQM should be taken LOW at READ command. For DQM should be taken LOW one cycle after the READ command. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM T0 T1 CLK READ ...
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... Temperature-Compensated Self Refresh (TCSR) On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator. Programming of the TCSR bits will have no effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature ...
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... Bits E5 and E6 of the extended mode register can be used to select the driver strength of the DQ outputs. This value should be set according to the application’s requirements. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 Register Definition ...
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... COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN ...
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... NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Load Mode Register The mode register is loaded via inputs A0–A12, BA0, and BA1. (See "Mode Register" on page 12 ...
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... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for required for the completion of any internal refresh in progress ...
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... Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 9 on page 23). ...
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... CL after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 12 on page 25 shows general timing for each possible CL setting. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM HIGH ROW ADDRESS BANK ADDRESS DON´ ...
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... CL -1. Figure 7 on page 16 shows CLs of two and three; data element either the last of a burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch archi- tecture ...
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... Figure 12: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Each READ command may be to any bank. DQM is LOW. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ NOP NOP BANK, COL n D OUT CLK READ ...
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... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
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... The READ command may be to any bank, and the WRITE command may be to any bank burst of one is used, then DQM is not required. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM met. Note that part of the row precharge time is T0 ...
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... The READ command may be to any bank, and the WRITE command may be to any bank. Figure 16: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Notes: 1. DQM is LOW. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ NOP NOP BANK, COL n DQ ...
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... Figure 17: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Notes: 1. DQM is LOW. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ NOP NOP BANK, COL n D OUT ...
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... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 20 on page 31. Data either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe- lined architecture and therefore does not require the 2n rule associated with a prefetch architecture ...
Page 31
... PRECHARGE command. An example is shown in Figure 23 on page 33. Data either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE ...
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... WRITE-to-READ CLK COMMAND ADDRESS Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW for illustration. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE WRITE WRITE WRITE ...
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... ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Figure 24: Terminating a WRITE Burst COMMAND ADDRESS PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK CK ≥ 15ns WRITE NOP PRECHARGE BANK ...
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... The device may not remain in the power-down state longer than the refresh period (64ms) since no REFRESH operations are performed in this mode. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK CKE HIGH CS# ...
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... CKE is LOW. CKE must be held LOW during deep power-down. Figure 27: Deep Power-Down Command CK# CK CKE CS# RAS# CAS# WE# A0–A12 BA0, BA1 PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM t CKS). See Figure 28 on page 36 CKS ( ( ) ...
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... Figure 29 on page 37 and Figure 30 on page 37). Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ta0 ...
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... In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed BL. READ commands access columns according to the programmed BL and sequence, just as in the normal mode of operation. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP ...
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... Concurrent Auto Precharge An access command (READ or WRITE second bank while an access command with auto precharge enabled on a first bank is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. ...
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... Figure 32: READ With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS Notes: 1. DQM is HIGH prevent D PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK READ - AP NOP NOP NOP BANK n Page READ with Burst of 4 ...
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... WRITE With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS Notes: 1. DQM is LOW. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM met, where WR begins when the WRITE to bank m is registered. The last CLK ...
Page 41
... H H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND of COMMAND 4. All states and sequences not shown are illegal or reserved. 5. Deep power-down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW. ...
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... Table 7, and according to Table 8 on page 44. Precharging: Row activating: Read w/auto- precharge enabled: Write w/auto- precharge enabled: PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WE# Command (Action COMMAND INHIBIT (NOP/Continue previous operation OPERATION (NOP/Continue previous operation) ...
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... May or may not be bank-specific; if all banks are to be precharged, all must valid state for precharging. 11. This command is BURST TERMINATE when CKE is HIGH. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Starts with registration of an AUTO REFRESH command and ends t t when RFC is met ...
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... Write w/auto- precharge enabled: 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WE# Command (Action COMMAND INHIBIT (NOP/Continue previous operation) ...
Page 45
... The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM met, where WR begins when the WRITE to bank m is regis- Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 46
... Output high voltage: Output low voltage: Input leakage current: Any input 0V ≤ V ≤ V (All other balls not under test = 0V Operating temperature Commercial Industrial PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Min –0.3 SS –0.3 SS –55 Symbol ...
Page 47
... Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH-to-ACTIVE command PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM -75 Symbol Min Max (3) 6 ...
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... Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out High-Z from PRECHARGE command PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Symbol t CCD t CKED t ...
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... No accesses in progress Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle Auto refresh current CKE = HIGH; CS# = HIGH Deep power-down PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM = 1.7V to 1.95V Symbol ...
Page 50
... Address and control inputs are stable; Data bus inputs are stable. Figure 35: Typical Self Refresh Current vs. Temperature 250 200 150 100 50 0 -40 PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM DD Low I Symbol Option “L” Full array, 85° Full array, 70° Full array, 45° ...
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... HZ defines the time at which the output achieves the open circuit condition not a reference to V High-Z. 11. AC timing and I point. If the input transition time is longer than enced at V PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Symbol Symbol . dependent on output loading and cycle rates ...
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... Deep power-down current is a nominal value at 25°C. This parameter is not tested. 31. There must be one PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM or V levels specifications are tested after the device is properly initialized. ...
Page 53
... CLK stable Notes: 1. PRE = PRECHARGE command AUTO REFRESH command, LMR = LOAD MODE REGISTER command. 2. Only NOPs or COMMAND INHIBITs may be issued during 3. At least one NOP or COMMAND INHIBIT is required during PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM ...
Page 54
... Precharge all All banks idle, enter active banks power-down mode Notes: 1. Violating refresh requirements during power-down may result in a loss of data. See Table 11 on page 47. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CKS NOP NOP ...
Page 55
... COLUMN m A11, A12 A10 BA0, BA1 BANK DQ Notes: 1. For this example and auto precharge is disabled and A11 = “Don’t Care.” See Table 11 on page 47. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP NOP NOP ...
Page 56
... A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required. See Table 11 on page 47. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM ...
Page 57
... AS AH BA0, BA1 BANK(S) High Precharge all active banks Notes: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required. See Table 11 on page 47. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CKS > t RAS ...
Page 58
... DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a manual PRECHARGE. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMH COLUMN m BANK t AC ...
Page 59
... AH ROW ADDR ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMS t CMH COLUMN m BANK OUT t LZ ...
Page 60
... DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a manual PRECHARGE. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP 3 NOP 3 READ t CMS t CMH COLUMN m BANK ...
Page 61
... AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by an auto precharge. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP 3 NOP 3 READ t CMS t CMH COLUMN m ENABLE AUTO PRECHARGE ...
Page 62
... ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK RCD - bank 0 t RAS - bank bank 0 t RRD Notes: 1. For this example PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP ACTIVE t CMH ROW COLUMN m ROW BANK 0 BANK ...
Page 63
... ADDR ROW COLUMN ROW A10 BA0, BA1 BANK BANK DQ t RCD Notes: 1. For this example PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP NOP t CMH Dout m D m+1 OUT t LZ All locations within same row CAS Latency Full-page burst does not self-terminate ...
Page 64
... ROW ADDR ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1. For this example PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM READ NOP NOP t CMS t CMH COLUMN m BANK OUT t LZ ...
Page 65
... BA0, BA1 RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by an auto precharge. 2. 15ns is required between <D quency. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP NOP t CMH BANK ...
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... AH ADDR ROW COLUMN ENABLE AUTO PRECHARGE ROW A10 BANK BA0, BA1 RCD t RAS t RC Notes: 1. For this example There must be one PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP NOP t CMH BANK ...
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... DQ t RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D 3. PRECHARGE command not allowed or PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP 3 NOP 3 WRITE t CMS ...
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... BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a manual PRECHARGE. 2. There must be one PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM NOP NOP WRITE NOP t CMS t CMH ...
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... ENABLE AUTO PRECHARGE ROW A10 BA0, BA1 BANK 0 BANK RCD - bank 0 t RAS - bank bank 0 t RRD Notes: 1. For this example PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP ACTIVE NOP t CMH ROW ROW BANK ...
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... ACTIVE NOP DQM ADDR ROW ROW A10 BA0, BA1 BANK DQ t RCD t Notes must be satisfied prior to PRECHARGE command. 2. Page left open; no PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMH t CMS COLUMN m BANK ...
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... NOP DQM ADDR ROW ROW A10 BA0, BA1 BANK DQ t RCD Notes: 1. For this example PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMS t CMH COLUMN m ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK ...
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... SMD ball pads. 3.2 6.4 0.8 TYP 0.8 TYP 6.4 Notes: 1. All dimensions are in millimeters. 2. Green packaging composition is available upon request. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 0.65 ±0.05 5 ±0.05 Ball 5.75 ±0. 11.5 ± ...
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... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 MT48H32M16LF_1.fm - Rev. J 2/08 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 0.65 ±0.05 Ball ±0. ...