CY7C09569V-83BBC Cypress Semiconductor Corp, CY7C09569V-83BBC Datasheet
CY7C09569V-83BBC
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CY7C09569V-83BBC Summary of contents
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... CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3 K/32 K × 36 FLEx36™ Synchronous Dual-Port Static RAM FLEx36™ Synchronous Dual-Port Static RAM 3 K/32 K × 36 FLEx36™ Synchronous Dual-Port Static RAM Features True dual-ported memory cells which allow simultaneous ■ access of the same memory location Two Flow-Through/Pipelined devices ■ ...
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... Functional Description The CY7C09569V and CY7C09579V are high-speed 3.3 V synchronous CMOS 16K and 32K × 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times ...
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... Word (18-bit) Operation ............................................. 27 Byte (9-bit) Operation ................................................ 27 Ordering Information ...................................................... 28 16K × 36 3.3 V Synchronous Dual-Port SRAM ......... 28 32K × 36 3.3 V Synchronous Dual-Port SRAM ......... 28 Ordering Code Definitions ......................................... 28 Package Diagrams .......................................................... 29 Sales, Solutions, and Legal Information ...................... 32 Worldwide Sales and Design Support ....................... 32 Products .................................................................... 32 PSoC Solutions ......................................................... 32 CY7C09569V CY7C09579V Page [+] Feedback ...
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... I/O26L 34 I/O25L 35 I/O24L 36 Notes 2. This pin is A14L for CY7C09579V. 3. This pin is A14R for CY7C09579V. Document Number: 38-06054 Rev. *D 144-pin Thin Quad Flatpack (TQFP) Top View CY7C09569V (16K × 36) CY7C09579V (32K × 36) CY7C09569V CY7C09579V 108 I/O33R I/O34R 107 106 I/O35R 105 A0R ...
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... CLKL ADSL CNTRSTL I/O26L I/O25L I/O19L VSS VSS I/O19R I/O25R I/O26R NC I/O7L I/O2L I/O2R I/O7R I/O6L I/O5L I/O3L I/O0L I/O0R I/3R VSS I/O4L VDD I/O1L I/O1R VDD CY7C09569V CY7C09579V I/O30R I/O32R A0R NC I/O27R I/O31R A1R NC A2R A5R A4R NC SIZE A7R A6R ...
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... Big Endian Pin. See Bus Matching for details Ground Input Power Input. DD Document Number: 38-06054 Rev. *D CY7C09579V CY7C09579V –100 –83 100 250 240 Description –A for 16K, A –A for 32K devices CY7C09569V CY7C09579V CY7C09579V Unit –67 67 MHz 8 ns 230 MAX Page [+] Feedback ...
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... Commercial – 0.01 1 Industrial – – Commercial – 150 200 Industrial – – – Test Conditions MHz CY7C09569V CY7C09579V Ambient Temperature V DD 3.3 V 165 +70 C 3.3 V 165 mV – +85 C CY7C09579V -83 -67 Unit 2.4 – ...
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... External AC Test Load Capacitance = 10 pF. 7. (Internal I/O pad Capacitance = 10 pF Test Load. Document Number: 38-06054 Rev. *D OUTPUT = 1 (b) Three-State Delay (Load 2) 3.0 V 90% 10 100 200 Capacitance (pF) (b) Load Derating Curve CY7C09569V CY7C09579V 3 590 435 90% 10% Page [+] Feedback ...
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... CY7C09569V CY7C09579V –67 Unit Max – 40 MHz – 67 MHz – ns – ns – ns – ns – ns – ns – – – ns – – ns – ...
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... This parameter is guaranteed by design, but it is not production tested. 11. Test conditions used are Load 2. Document Number: 38-06054 Rev. *D CY7C09579V –100 –83 Min Max Min Max Min – 2 – – 30 – 35 – 9 – 10 CY7C09569V CY7C09579V –67 Unit Max – ns – – Page [+] Feedback ...
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... n+1 t OHZ [12, 13, 14, 15 CL2 n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ t OLZ ...
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... Cycle Cycle [16, 17, 18, 19 CD2 CD2 t CLKZ 1st Cycle following the next rising edge of the clock. IH only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V A n n+1 n+1 1st 2nd Cycle Cycle n+1 t CD2 n 2nd Cycle ...
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... CD2 SC CKHZ CKLZ [22, 23, 24, 25, 26] NO MATCH t CD1 NO MATCH t CWDD VALID , CNTRST = for the left port, which is being written to. IH CY7C09569V CY7C09579V CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not valid CWDD CCS Page [+] Feedback ...
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... During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 38-06054 Rev. *D [27, 28, 29, 30 n+1 n CD2 CKHZ OPERATION constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V A A n+3 n CD2 CKLZ Q WRITE READ Page n+3 [+] Feedback ...
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... IH 34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 38-06054 Rev. *D [31, 32, 33, 34 n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE CY7C09569V CY7C09579V A A n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback ...
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... Word 2nd Word D D n+2 n WRITE WRITE READ Operation 2nd Cycle 1st Cycle 2nd Cycle only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V n+3 n+4 n+4 n+3 2nd Word 1st Word Q Q n+3 n+3 t CD2 t DC READ ...
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... CD1 Q n+1 t CKHZ NO READ OPERATION [42 , 43, 46, 47, 48 n+1 n+2 n n+2 n OHZ READ WRITE constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V n+3 n CD1 CD1 Q n CKLZ DC WRITE READ A A n+4 n CD1 t CD1 Q n+4 ...
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... n+1 n+1 2nd Word 1st Word t CKHZ Q n 2nd Word No WRITE WRITE Operation 1st Cycle 2nd Cycle only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V n+1 n+2 n CD1 CD1 Q Q n+1 n CKLZ READ READ 1st Cycle 2nd Cycle ...
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... SAD HAD t t SCN HCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER [56] t SAD t SCN Q Q n+1 COUNTER HOLD READ WITH COUNTER CY7C09569V CY7C09579V Q Q n+2 n+3 READ WITH COUNTER t HAD t HCN Q Q n+2 n+3 n READ DC DC WITH t t CD1 COUNTER ...
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... CNTRST = V IL 58. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V Document Number: 38-06054 Rev n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and CNTRST CY7C09569V CY7C09579V [57, 58 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . Page [+] Feedback ...
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... No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 63. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA during a valid WRITE cycle. Document Number: 38-06054 Rev. *D [59, 60, 61, 62, 63 CD2 Q t CKLZ READ READ ADDRESS 0 ADDRESS 1 CY7C09569V CY7C09579V ...
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... No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 68. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA during a valid WRITE cycle. Document Number: 38-06054 Rev. *D [64, 65, 66, 67, 68 CD1 Q 0 WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09569V CY7C09579V n n ...
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... SCN HCN CA2 READ WITH t COUNTER DC [69, 70, 72] A n+1 t SAD n+1 READ WITH COUNTER is extended by 1 cycle. N CY7C09569V CY7C09579V A A n+2 n+1 HAD Q Q n+1 n+2 COUNTER READ WITH COUNTER HOLD A A n+3 n+2 t HAD t t HCN SCN Q Q n+2 ...
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... R/W ADS CNTEN CNTRST CY7C09569V CY7C09579V Operation [76] Deselected Write [76] Read Outputs Disabled Mode Operation Reset Counter Reset Load Address Load into Counter Hold + External Address Blocked - Read Counter Address Readout Hold External Address Blocked - Counter Disabled Increment Counter Increment Page [+] Feedback ...
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... DQ DQ 27R–35R 18R–26R [81] I/O Pins used on 1st Cycle I/O 3L–17L I/O 3R–17R I/O 2R–17R I/O 0R–8R I/O I/O I/O CY7C09569V CY7C09579V I/O Pins used I/O 0R–35R I/O 0R–17R I/O 0R–8R Data on 3rd Cycle Data on 4th Cycle - - - - DQ DQ 18R–26R 27R– ...
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... They must be forced either HIGH or LOW. Document Number: 38-06054 Rev. *D Bus Match Operation The right port of the CY7C09569V/09579V 16K/32Kx36 dual-port SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines) ...
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... An internal sub-counter automatically increments the right port multiplexer control when Little or Big Endian operation is in effect. When transferring data in byte (9-bit) bus match format, the unused I/O pins (I/O ) are three-stated. 9RQ–35R CY7C09569V CY7C09579V Page [+] Feedback ...
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... Temperature Range Commercial X = Pb-free (RoHS Compliant) Package Type 144-pin TQFP BB = 172-ball BGA Speed Grade: XXX = 83 MHz or 100 MHz Depth 16K 32K 5 = Width: × Sync 7C = Dual Port SRAM CY = Cypress Device CY7C09569V CY7C09579V Operating Range Commercial Operating Range Commercial Commercial Page [+] Feedback ...
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... Package Diagrams Document Number: 38-06054 Rev. *D Figure 3. 144-pin TQFP (20 × 20 × 1.4 mm) CY7C09569V CY7C09579V 51-85047 *C Page [+] Feedback ...
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... Document Number: 38-06054 Rev. *D Figure 4. 172-ball FBGA (15 × 15 × 1.25 mm) CY7C09569V CY7C09579V 51-85114 *C Page [+] Feedback ...
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... Document History Page Document Title: CY7C09569V/CY7C09579V 3 K/32 K × 36 FLEx36™ Synchronous Dual-Port Static RAM Document Number: 38-06054 Orig. of REV. ECN NO. Issue Date Change ** 110213 12/16/01 *A 122304 12/27/02 *B 349775 See ECN *C 2897215 03/22/10 RAME *D 3110406 12/14/2010 ADMU Document Number: 38-06054 Rev. *D Description of Change ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06054 Rev. *D FLeX36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised December 18, 2010 CY7C09569V CY7C09579V PSoC Solutions psoc.cypress.com/solutions PSoC 1 ...