TDA16888GGEGXT Infineon Technologies, TDA16888GGEGXT Datasheet
TDA16888GGEGXT
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TDA16888GGEGXT Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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High Performance Power Combi Controller 1 Overview 1.1 Features PFC Section – IEC 1000-3 compliant – Additional operation mode as auxiliary power supply – Fast, soft switching totem pole gate drive (1 A) – Dual loop control (average current and ...
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Special Features – High power factor – Typical 50 A start-up supply current – Low quiescent current (15 mA) – Undervoltage lockout with internal stand-by operation – Internally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz – ...
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P-DIP-20-5 PFC IAC REF PFC CC 3 PFC CS 4 GND S 5 PFC CL 6 GND 7 PFC OUT PWM OUT 10 Figure 1 Pin Configuration (top view) Version 2.0 PFC IAC ...
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Pin Definitions and Functions Pin No. Symbol 1 PFC IAC 2 V REF 3 PFC CC 4 PFC CS 5 GND S 6 PFC CL 7 GND 8 PFC OUT PWM OUT 11 PWM CS ...
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Block Diagram Figure 2 Version 2 TDA 16888 28 Feb 2000 ...
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Functional Description Power Supply The TDA 16888 is protected against overvoltages typically above 17 internal V Zener diode Z3 at pin 9 ( ESD circuitry. By means of its power management the TDA 16888 will switch ...
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Both PFC and PWM section are equipped with a peak current limitation, which is realized by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS) respectively. When being activated this current limitation will ...
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PFC Section At normal operation the PFC section operates with dual loop control. An inner loop, which includes OP2, C1, FF1 and the PFC’s driver, controls the shape of the line current by average current control enabling either continuous or ...
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The pulse-width-modulation of the PWM section is trailing edge modulated according to V the PWM ramp signal PWM RMP pin 14 (PWM IN) (see Figure 18). In contrast to the PFC section, however, the pulse- width-modulation of the PWM section ...
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Functional Block Description Gate Drive Both PFC and PWM section use fast totem pole gate drives at pin 8 (PFC OUT) and pin 10 (PWM OUT) respectively, which are designed to avoid cross conduction currents and which are equipped ...
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The oscillator can be synchronized with an external clock signal supplied at pin 12 (SYNC). As long as this clock signal is H the oscillator’s triangular signal interrupted and its clock signal CLK OSC is H (see Figure 19 and ...
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Current Amplifier OP2 Being part of the inner loop the error amplifier OP2 controls the shape of the line current by comparison of the controlled current is achieved by setting the pulse width of the PFC gate drive in conjunction ...
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Comparator C1 The comparator C1 serves to adjust the duty cycle of the PFC gate drive. This is achieved by comparison of the output voltage of OP2 given at pin 3 (PFC CC) and the voltage ramp of the oscillator. ...
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Comparator C8 The control of the pulse width modulation of the PWM section is taken over by comparator C8 as soon as the soft start is finished. This is achieved by comparison of the PWM output voltage at pin 14 ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings T = – Parameter# V supply voltage CC Zener current voltage REF ROSC voltage SYNC voltage PFC FB voltage PFC IAC voltage AUX VS voltage ...
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Absolute Maximum Ratings (cont’ – Parameter# Storage temperature Thermal resistance Thermal resistance Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. ...
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Characteristics Supply Section Parameter 1) Zener voltage Zener current Quiescent supply current Supply current 1) See Figure 3 2) Design characteristics (not meant for production testing) Note: The electrical characteristics involve the spread of values guaranteed within the specified ...
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Undervoltage Lockout Parameter Power up, rising voltage 1) threshold Power down, falling voltage 1) threshold Power up, threshold current 1) See Figure ensure the voltage fallback of pin PFC CL is disabled. Internal Voltage Reference Parameter Trimmed ...
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External Voltage Reference Parameter Buffered output voltage Line regulation Load regulation Maximum output 1) current 1) Short circuit current Shutdown hysteresis, rising voltage threshold Shutdown hysteresis, falling voltage threshold Shutdown delay 1) See Figure 4 2) Design characteristics (not meant ...
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PFC Section Parameter 1) Max duty cycle Multiplier throttling (OTA2), threshold 2) voltage Overvoltage protection (C6), rising voltage threshold Overvoltage protection (C6), falling voltage threshold Overvoltage protection (C6), turn-off delay Broken wire detection (C2), threshold voltage Voltage sense, input current ...
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Multiplier Parameter Input current Input voltage Exponential function, threshold voltage Maximum output current 3) Output current 1) Design characteristics (not meant for production testing) 2) For input voltages below this threshold the multiplier output current remains constant. For input voltages ...
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Operational Transconductance Amplifier (OTA1) Parameter Auxiliary power supply, 1) threshold voltage Input current Output current 1) For input voltages below this threshold the output current is linearly increasing until at ca. 4.8 V the maximum output current is reached. Operational ...
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Voltage Amplifier (OP1) Parameter Offset voltage Input current Open loop gain Input voltage range Voltage sense, threshold voltage Output, maximum voltage Output, minimum voltage Output, short circuit source current Output, short circuit sink current 1) Guaranteed by wafer test 2) ...
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Current Amplifier (OP2) Parameter Offset voltage Input current Open loop gain Gain bandwidth product Phase margin Common mode voltage range Clamped input voltage, upper threshold (D2, D3) Clamped input voltage, lower threshold (D1) Output, maximum voltage Output, minimum voltage Output, ...
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PWM Section Parameter Undervoltage protection (C4), threshold voltage Bias control (C5), rising voltage threshold Bias control (C5), falling voltage threshold Softstart ( charging current Softstart, maximum voltage Input voltage PWM IN – GND resistance Ramp (OP3), voltage ...
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Gate Drive (PWM and PFC Section) Parameter Output, minimum voltage Output, maximum voltage 1) Rise time Fall time Output current, rising edge Output current, falling edge 1) See Figure 13 2) Transient reference value 3) The gate driver’s output performance ...
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VCC Figure 3 Undervoltage Lockout Hysteresis and Zener Diode Overvoltage Protection - VREF - Figure 4 Foldback Characteristic of Pin 2 ( Version 2 ...
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OUT 100 10 10 Figure 5 PFC/PWM Frequency 100 % D on, PFC, max Figure 6 Maximum PFC Duty Cycle Version 2.0 100 100 200 30 TDA 16888 AED02464 500 k R ...
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A V PFC VC PFC CCS 400 300 200 100 0 0 Figure 7 Multiplier Linearity 500 A PFC CCS 400 300 200 100 0 0 Figure 8 Multiplier Dynamic Version 2 ...
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A > 300 PFC IAC PFC CCS 400 300 200 100 0 5.0 Figure 9 Multiplier Throttling by OTA2 100 dB A PFC Figure 10 Open Loop Gain and ...
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A PFC CC 100 Figure 11 Open Loop Gain and Phase Characteristic of Current Amplifier OP2 PWM ...
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V V PFC OUT Figure 13 Rising Edge of Driver Output 150 100 Figure 14 Power Dissipation of Single Gate Driver at Version 2.0 0.1 0.2 ...
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P D 400 300 200 100 0 0 Figure 15 Power Dissipation of Single Gate Driver 0.8 0.6 0.4 0 Figure 16 Power Dissipation of Single Gate Driver at Version 2.0 ...
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P D 1.0 0 Figure 17 Power Dissipation of Single Gate Driver at Version 2 ...
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V OSC CLK OSC CLK OUT V PFC RMP V PFC OUT V PWM RMP V BC PWM OUT Figure 18 Timing Diagram without Synchronization Version 2.0 V PFC CC V PWM IN t on, max 37 TDA ...
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V OSC CLK OSC CLK OUT V PFC RMP V PFC OUT V PWM RMP V PWM OUT Figure 19 Timing Diagram with Synchronization ( Version 2.0 V SYNC V PFC CC t on, max V BC on, ...
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V OSC CLK OSC CLK OUT V PFC RMP V PFC OUT V PWM RMP V PWM OUT Figure 20 Timing Diagram with Synchronization ( Version 2.0 V SYNC t on, max V PWM ...
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Package Outlines P-DIP-20-5 (Plastic Dual In-line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Version 2.0 40 TDA 16888 Dimensions Feb 2000 ...
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P-DSO-20-1 (Plastic Dual Small Outline) 1.27 +0.15 2) 0.35 20 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Sorts of Packing Package ...
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