XC5VSX50T-1FF665C Xilinx Inc, XC5VSX50T-1FF665C Datasheet - Page 39

FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA

XC5VSX50T-1FF665C

Manufacturer Part Number
XC5VSX50T-1FF665C
Description
FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-1FF665C

Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
52224
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
4866048
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Table 59: Output Delay Measurement Methodology (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
HSTL, Class III & IV, with DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III & IV, 1.8V, with DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
SSTL, Class I & II, 2.5V, with DCI
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
C
Per PCI specifications.
Per PCI-X specifications.
The value given is the differential input voltage.
REF
is the capacitance of the probe, nominally 0 pF.
Description
www.xilinx.com
HSTL_III_18
SSTL18_I
LVDS_25
HSTL_III_DCI_18,
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_IV_18
SSTL18_II
SSTL2_I
SSTL2_II
LVDS_25
BLVDS_25
LDT_25
LVPECL_25
LVDCI_33, HSLVDCI_33
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
HSTL_III_DCI, HSTL_IV_DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI, SSTL2_II_DCI
GTL_DCI
GTLP_DCI
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard
Attribute
R
100
100
100
100
100
(Ω)
1M
1M
1M
1M
25
50
25
50
25
50
25
50
25
50
50
50
50
50
50
50
50
REF
C
(pF)
REF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)
V
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
MEAS
(V)
0
0
0
0
0
0.9
1.1
0.9
1.1
0.8
1.1
0.9
1.0
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
(4)
(4)
(4)
(4)
(4)
V
1.25
1.25
0.75
1.25
(V)
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.2
1.2
0.6
1.5
0.9
1.8
0.9
1.2
1.5
REF
0
0
0
0
0
0
39

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