LFEC6E-3F256C LATTICE SEMICONDUCTOR, LFEC6E-3F256C Datasheet
LFEC6E-3F256C
Specifications of LFEC6E-3F256C
Available stocks
Related parts for LFEC6E-3F256C
LFEC6E-3F256C Summary of contents
Page 1
LatticeECP/EC Family Data Sheet DS1000 Version 02.7, February 2008 ...
Page 2
... LatticeECP devices only. © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 3
... Lattice Semiconductor Introduction The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP- DSP™ ...
Page 4
... The LatticeECP/EC devices use 1.2V as their core volt- age. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 5
... Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeEC Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysCONFIG Programming Port (includes dedicated and dual use pins) Programmable Functional Unit (PFU) Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level) ...
Page 6
... Lattice Semiconductor PFU and PFF Blocks The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks ...
Page 7
... Lattice Semiconductor Figure 2-4. Slice Diagram From M1 Routing Control Signals CE selected and CLK inverted per LSR slice in routing Interslice signals are not shown Table 2-1. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose Input Multi-purpose Input ...
Page 8
... Lattice Semiconductor Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes PFU Slice ...
Page 9
... Lattice Semiconductor Figure 2-5. Distributed Memory Primitives SPR16x2 AD0 AD1 AD2 AD3 DI0 DI1 WRE CK ROM16x1 AD0 AD1 AD2 AD3 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. ...
Page 10
... Lattice Semiconductor Routing There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). ...
Page 11
... Lattice Semiconductor Secondary Clock Sources LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7. ...
Page 12
... Lattice Semiconductor Figure 2-8. Per Quadrant Primary Clock Selection 20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing 4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant 1. Smaller devices have fewer PLL related lines. Figure 2-9. Per Quadrant Secondary Clock Selection 20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals Figure 2-10 ...
Page 13
... Lattice Semiconductor grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the t allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider ...
Page 14
... Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing I PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock CLKFB (PIN or logic) RST I “1” to reset PLL CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) ...
Page 15
... Lattice Semiconductor Figure 2-14. DCS Waveforms CLK0 CLK1 SEL DCSOUT sysMEM Memory The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Confi ...
Page 16
... Lattice Semiconductor Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
Page 17
... Lattice Semiconductor Figure 2-16. Memory Core Reset RSTA RSTB GSRN For further information about sysMEM EBR block, please see the the list of technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-17 ...
Page 18
... Lattice Semiconductor decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul- tiply-accumulators. sysDSP Block Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds ...
Page 19
... Lattice Semiconductor Table 2-7. Maximum Number of Elements in a Block Width of Multiply MULT MAC MULTADD MULTADDSUM Some options are available in four elements. The input register in all the elements can be directly loaded or can be loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the ‘ ...
Page 20
... Lattice Semiconductor Figure 2-20. MAC sysDSP Element Shift Register B In Multiplicand n Multiplier n n Input Data Register B n SignedAB Input Register Addn Input Register Accumsload Input Register Shift Register B Out MULTADD sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and A2 ...
Page 21
... Lattice Semiconductor MULTADDSUM sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block ...
Page 22
... Lattice Semiconductor Signed and Unsigned with Different Widths The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached ...
Page 23
... Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the IPexpress configuration tool, included with the ispLEVER design tool suite. IPexpress has options to configure each DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Mathworks to support instantiation in the Simulink tool, which is a Graphical Simulation Environment ...
Page 24
... Lattice Semiconductor For further information about the sysDSP block, please see the list of technical information at the end of this data sheet. Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O buffer, and receives input from the buffer ...
Page 25
... Lattice Semiconductor Table 2-12. PIO Signal List Name CE0, CE1 Control from the core CLK0, CLK1 Control from the core LSR Control from the core GSRN Control from routing INCK Input to the core DQS Input to PIO INDD Input to the core INFF ...
Page 26
... Lattice Semiconductor Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-26 shows the diagram of the input register block. Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal fi ...
Page 27
... Lattice Semiconductor Figure 2-27. Input Register DDR Waveforms DI (In DDR Mode) DQS DQS Delayed D0 D2 Figure 2-28. INDDRXB Primitive Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-29 shows the diagram of the Output Register Block. In SDR mode, ONEG0 feeds one of the fl ...
Page 28
... Lattice Semiconductor Figure 2-29. Output Register Block ONEG0 From Routing OPOS0 CLK1 Figure 2-30. ODDRXB Primitive Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block. In SDR mode, ONEG1 feeds one of the fl ...
Page 29
... Lattice Semiconductor Figure 2-31. Tristate Register Block TD ONEG1 From Routing OPOS1 CLK1 Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from the programmable DQS pin ...
Page 30
... Lattice Semiconductor Figure 2-32. DQS Local Bus. Delay Control Bus Polarity Control Bus DQS Bus DQS DQS Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus LatticeECP/EC Family Data Sheet PIO Input Register Block ( 5 Flip Flops) To Sync. Reg. ...
Page 31
... Lattice Semiconductor Polarity Control Logic In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system Clock (during the READ cycle) is unknown. The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is used ...
Page 32
... Lattice Semiconductor Figure 2-34. LatticeECP/EC Banks V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND LatticeECP/EC devices contain two types of sysI/O buffer pairs. 1. Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be confi ...
Page 33
... Lattice Semiconductor Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when V After the POR signal is deactivated, the FPGA core logic becomes active the user’s responsibility to ensure that all other V banks are active with valid input logic levels to properly control the output logic states of all the CCIO I/O banks that are critical to the application ...
Page 34
... Lattice Semiconductor Table 2-14. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II, III HSTL15 Class I, III SSTL3 Class I, II ...
Page 35
... Lattice Semiconductor be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. ...
Page 36
... Lattice Semiconductor Oscillator Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configura- tion. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 2- 15 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design pro- cess, the following sequence takes place: 1 ...
Page 37
... LVCMOS and LVTTL only. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 38
... Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Leakage IL Input or I/O High Leakage IH I I/O Active Pull-up Current PU I I/O Active Pull-down Current PD I Bus Hold Low sustaining current BHLS I Bus Hold High sustaining current V BHHS I Bus Hold Low Overdrive current ...
Page 39
... Lattice Semiconductor Supply Current (Standby) Symbol Parameter I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current CCPLL I Bank Power Supply Current CCIO I V Power Supply Current CCJ CCJ 1. For further information about supply current, please see the list of technical documentation at the end of this data sheet. ...
Page 40
... Lattice Semiconductor Initialization Supply Current Symbol Parameter I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current CCPLL I Bank Power Supply Current CCIO I V Power Supply Current CCJ CCJ 1. Until DONE signal is active. 2. For further information about supply current, please see the list of technical documentation at the end of this data sheet. ...
Page 41
... Lattice Semiconductor sysI/O Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.135 LVCMOS 2.5 2.375 LVCMOS 1.8 1.71 LVCMOS 1.5 1.425 LVCMOS 1.2 1.14 LVTTL 3.135 PCI 3.135 SSTL18 Class I 1.71 SSTL2 Class I, II 2.375 SSTL3 Class I, II 3.135 HSTL15 Class I 1.425 HSTL15 Class III 1 ...
Page 42
... Lattice Semiconductor sysI/O Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.35V PCI -0.3 0.3V CCIO SSTL3 class I -0 ...
Page 43
... Lattice Semiconductor sysI/O Differential Electrical Characteristics LVDS Parameter Symbol Parameter Description V V Input voltage INP, INM V Differential input threshold THD V Input common mode voltage CM I Input current IN V Output high voltage for Output low voltage for Output voltage differential OD Change in V between high and OD Δ ...
Page 44
... Lattice Semiconductor Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow- able single-ended output classes (class I and class II) are supported in this mode. LVDS25E The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs ...
Page 45
... Lattice Semiconductor BLVDS The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
Page 46
... Lattice Semiconductor LVPECL The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...
Page 47
... Lattice Semiconductor RSDS The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
Page 48
... Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 32-bit decoder 64-bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register-to-Register Performance Function Basic Functions 16 bit decoder 32 bit decoder 64 bit decoder 4:1 MUX ...
Page 49
... Lattice Semiconductor Derating Timing Tables Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and voltage multiply the noted numbers with the derating factors provided below ...
Page 50
... Lattice Semiconductor LatticeECP/EC External Switching Characteristics Parameter Description General I/O Pin Parameters (Using Primary Clock without PLL) Clock to Output - PIO Output Register Clock to Data Setup - PIO Input Register Clock to Data Hold - PIO Input Register Clock to Data Setup - PIO Input 7 t SU_DEL ...
Page 51
... Lattice Semiconductor LatticeECP/EC External Switching Characteristics (Continued) Parameter Description t Data Valid Before DQS DQVBS t Data Valid After DQS DQVAS f DDR Clock Frequency MAX_DDR 6 Primary and Secondary Clock 2 f Frequency for Primary Clock Tree MAX_PRI Clock Pulse Width for Primary t W_PRI Clock ...
Page 52
... Lattice Semiconductor LatticeECP/EC Internal Switching Characteristics Parameter PFU/PFF Logic Mode Timing t LUT4 Delay ( Inputs to F Output) LUT4_PFU t LUT6 Delay ( Inputs to OFX Output) LUT6_PFU t Set/Reset to Output of PFU LSR_PFU t Clock to Mux (M0,M1) Input Setup Time SUM_PFU t Clock to Mux (M0,M1) Input Hold Time HM_PFU ...
Page 53
... Lattice Semiconductor LatticeECP/EC Internal Switching Characteristics (Continued) Parameter Clock Enable Setup Time to EBR Output t SUCE_EBR Register t Clock Enable Hold Time to EBR Output Register HCE_EBR Reset To Output Delay Time from EBR Output t RSTO_EBR Register PLL Parameters t Reset Recovery to Rising Clock RSTREC t Reset Signal Setup Time ...
Page 54
... Lattice Semiconductor Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] DO[1:0] CK WRE AD AD[3:0] D DI[1:0] DO[1:0] Old Data Old Data 3-18 DC and Switching Characteristics LatticeECP/EC Family Data Sheet ...
Page 55
... Lattice Semiconductor EBR Memory Timing Diagrams Figure 3-8. Read/Write Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-9. Read/Write Mode with Input and Output Registers ...
Page 56
... Lattice Semiconductor Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only) ...
Page 57
... Lattice Semiconductor LatticeECP/EC Family Timing Adders Buffer Type Input Adjusters LVDS25 LVDS BLVDS25 BLVDS LVPECL33 LVPECL HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18_III HSTL_18 class III HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class II HSTL18D_III Differential HSTL 18 class III HSTL15_I HSTL_15 class I ...
Page 58
... Lattice Semiconductor LatticeECP/EC Family Timing Adders Buffer Type HSTL15_II HSTL_15 class II HSTL15_III HSTL_15 class III HSTL15D_I Differential HSTL 15 class I HSTL15D_III Differential HSTL 15 class III SSTL33_I SSTL_3 class I SSTL33_II SSTL_3 class II SSTL33D_I Differential SSTL_3 class I SSTL33D_II Differential SSTL_3 class II SSTL25_I SSTL_2 class I ...
Page 59
... Lattice Semiconductor sysCLOCK PLL Timing Parameter Description f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter ...
Page 60
... Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t Clock to Dout in Flowthrough Mode CODO t CS[0:1] Setup Time to CCLK SUCS t CS[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
Page 61
... Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications (Continued) Parameter t CSSPIN Active Setup Time SOE t CSSPIN Low to First Clock Edge Setup Time CSPID f Max Frequency for SPI MAXSPI t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK HSPI Timing v ...
Page 62
... Lattice Semiconductor Figure 3-12. sysCONFIG Parallel Port Read Cycle 1 CCLK CS1N CSN WRITEN BUSY D[0: Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. Figure 3-13. sysCONFIG Parallel Port Write Cycle 1 CCLK CS1N CSN WRITEN ...
Page 63
... Lattice Semiconductor Figure 3-14. sysCONFIG Master Serial Port Timing CCLK (output) DIN DOUT Figure 3-15. sysCONFIG Slave Serial Port Timing CCLK (input) DIN DOUT Figure 3-16. Power-On-Reset (POR) Timing CCAUX INITN DONE 2 CCLK 3 CFG[2:0] 1. Time taken from Device Master Mode. 3. The CFG pins are normally static (hard wired). ...
Page 64
... Lattice Semiconductor Figure 3-17. Configuration from PROGRAMN Timing PROGRAMN t DPPINIT INITN t DINITD DONE CCLK CFG[2:0] USER I/O 1. The CFG pins are normally static (hard wired) Figure 3-18. Wake-Up Timing PROGRAMN INITN DONE CCLK USER I/O Figure 3-19. sysCONFIG SPI Port Sequence ...
Page 65
... Lattice Semiconductor JTAG Port Timing Specifications Symbol f TCK clock frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time BTS t TCK [BSCAN] hold time ...
Page 66
... Lattice Semiconductor Switching Test Conditions Figure 3-21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-21. Output Test Load, LVTTL and LVCMOS Standards Table 3-6 ...
Page 67
... TMS TCK © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 68
... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name TDI TDO V CCJ Configuration Pads (used during sysCONFIG) CFG[2:0] INITN PROGRAMN DONE CCLK BUSY/SISPI CSN CS1N WRITEN D[7:0]/SPID[0:7] DOUT/CSON DI/CSSPIN LatticeECP/EC Family Data Sheet I/O Test Data in pin. Used to load data into device using 1149.1 state machine. ...
Page 69
... Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] Notes: 1. “n” Row/Column PIC number 2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR data (DQ) pins may not be available. 3. PIC numbering defi ...
Page 70
... Lattice Semiconductor Pin Information Summary LFEC1 100- 144- Pin Type TQFP TQFP Single Ended User 67 97 I/O Differential Pair User 29 46 I/O Dedicated 13 13 Configu- ration Muxed 48 48 TAP 5 5 Dedicated (total 80 110 without supplies CCAUX CCPLL Bank0 1 2 Bank1 ...
Page 71
... Lattice Semiconductor Pin Information Summary (Cont.) Pin Type Single Ended User I/O Differential Pair User I/O Dedicated Configuration Muxed TAP Dedicated (total without supplies CCAUX V CCPLL Bank0 Bank1 Bank2 Bank3 V CCIO Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 NC Bank0 Bank1 Bank2 ...
Page 72
... Lattice Semiconductor Power Supply and NC Connections Signals 100 TQFP VCC 12, 64 VCCIO0 100 VCCIO1 86 VCCIO2 73 VCCIO3 56 VCCIO4 38 VCCIO5 26 VCCIO6 24 VCCIO7 2 VCCJ 18 VCCAUX 37, 87 VCCPLL — GND, GND0-GND7 1, 14, 25, 35, 51, 68, 74 — LatticeECP/EC Family Data Sheet 144 TQFP 208 PQFP EC1, EC3: 13, 92, 99 ...
Page 73
... Lattice Semiconductor Power Supply and NC Connections (Cont.) Signals VCC J16, J7, K16, K17, K6, K7, L17, L6, M17, M6, N16, N17, N6, N7, P16, P7, J6, J17, P6, P17 VCCIO0 G11, H10, H11, H9 VCCIO1 G12, H12, H13, H14 VCCIO2 J15, K15, L15, L16 VCCIO3 M15, M16, N15, P15 ...
Page 74
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 100 TQFP Pin Pin Number Function Bank GND0 1* - GND7 2 VCCIO7 7 3 PL2A 7 4 PL2B 7 5 PL3A 7 6 PL3B 7 7 PL4A 7 8 PL4B 7 9 PL5A 7 10 PL5B 7 11 XRES 6 12 VCC - 13 TCK 6 14 GND - 15 TDI ...
Page 75
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.) Pin Pin Number Function Bank 41 PB11A 4 42 PB11B 4 43 PB12B 4 44 PB13A 4 45 PB13B 4 46 PB14A 4 47 PB14B 4 48 PB15B 4 49 PB16B 4 50 PB17B 4 GND3 51* - GND4 52 PR10B 3 53 PR10A 3 54 PR9B ...
Page 76
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.) Pin Pin Number Function Bank 82 PT11B 1 83 PT11A 1 84 PT10B 1 85 PT10A 1 86 VCCIO1 1 87 VCCAUX - 88 PT9B 0 89 GND0 0 90 PT9A 0 91 PT8B 0 92 PT8A 0 93 PT7B 0 94 PT6B 0 95 PT6A ...
Page 77
... Lattice Semiconductor LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP LFEC1 Pin Number Pin Function Bank LVDS Dual Function 1 VCCIO7 7 2 PL2A 7 T VREF2_7 3 PL2B 7 C VREF1_7 4 PL3A PL3B PL4A PL4B PL5A 7 T PCLKT7_0 9 PL5B 7 C PCLKC7_0 10 XRES VCC - 14 TCK 6 15 ...
Page 78
... Lattice Semiconductor LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.) LFEC1 Pin Number Pin Function Bank LVDS Dual Function 50 PB8B 5 C VREF1_5 51 PB9A 5 T PCLKT5_0 52 GND5 5 53 PB9B 5 C PCLKC5_0 54 VCCAUX - 55 VCCIO4 4 56 PB10A PB10B PB11A 4 T VREF1_4 59 PB11B PB12A ...
Page 79
... Lattice Semiconductor LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.) LFEC1 Pin Number Pin Function Bank LVDS Dual Function 99 VCC - 100 PR5B 2 C PCLKC2_0 101 PR5A 2 T PCLKT2_0 102 PR4B 2 C 103 PR4A 2 T 104 PR3B 2 C 105 PR3A 2 T 106 ...
Page 80
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP Pin Number Pin Function Bank GND0 1* GND7 2 VCCIO7 3 PL2A 4 PL2B PL3A 16 PL3B 17 PL4A PL4B 20 PL5A 21 PL5B XRES VCC 27 TCK 28 GND 29 TDI 30 TMS 31 TDO 32 VCCJ 33 PL7A 34 PL7B 35 PL8A 36 PL8B 37 VCCIO6 38 PL9A 39 PL9B 40 PL10A ...
Page 81
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function Bank 43 PL11A 44 PL11B 45 PL12A 46 PL12B 47 PL13A 48 PL13B 49 PL14A 50 PL14B 51 VCCIO6 GND5 52* GND6 53 VCCIO5 PB2A 66 PB2B 67 PB3A 68 PB3B 69 PB4A 70 PB4B 71 PB5A PB5B 74 VCCIO5 75 PB6A 76 PB6B 77 PB7A 78 PB7B 79 PB8A ...
Page 82
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function Bank 85 VCCIO4 86 PB10A 87 PB10B 88 PB11A 89 PB11B 90 PB12A 91 PB12B 92 PB13A 93 GND4 94 PB13B 95 PB14A 96 PB14B 97 PB15A 98 PB15B 99 PB16A 100 PB16B 101 PB17A 102 PB17B 103 NC 104 VCCIO4 GND3 105* ...
Page 83
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function Bank 127 CFG0 128 VCC 129 PROGRAMN 130 CCLK 131 INITN 132 GND 133 DONE 134 GND 135 VCC 136 NC 137 PR5B 138 NC 139 PR5A 140 PR4B ...
Page 84
... Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) Pin Number Pin Function Bank 169 PT13A 170 PT12B 171 PT12A 172 PT11B 173 PT11A 174 PT10B 175 PT10A 176 VCCIO1 177 VCCAUX 178 PT9B 179 GND0 180 PT9A 181 PT8B ...
Page 85
... Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP LFECP6/LFEC6 Pin Number Pin Function Bank GND0 1* GND7 2 VCCIO7 3 PL2A 4 PL2B PL3B 8 PL4A 9 PL4B 10 PL5A 11 PL5B 12 PL6A 13 VCCIO7 14 PL6B 15 PL7A 16 PL7B 17 PL8A 18 GND7 19 PL8B 20 PL9A 21 PL9B 22 VCCAUX 23 XRES 24 VCC 25 GND 26 VCC 27 TCK ...
Page 86
... Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number Pin Function Bank 43 PL24A 44 PL24B 45 PL25A 46 PL25B 47 PL26A 48 PL26B 49 PL27A 50 PL27B 51 VCCIO6 GND5 52* GND6 53 VCCIO5 54 PB2A 55 PB2B 56 PB3A 57 PB3B 58 PB4A 59 PB4B 60 PB5A 61 PB5B 62 PB6A 63 PB6B 64 VCCIO5 65 PB10A 66 PB10B ...
Page 87
... Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number Pin Function Bank 85 VCCIO4 86 PB18A 87 PB18B 88 PB19A 89 PB19B 90 PB20A 91 PB20B 92 PB21A 93 GND4 94 PB21B 95 PB22A 96 PB22B 97 PB23A 98 PB23B 99 PB24A 100 PB24B 101 PB25A 102 PB25B 103 PB33A 104 VCCIO4 ...
Page 88
... Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number Pin Function Bank 127 CFG0 128 VCC 129 PROGRAMN 130 CCLK 131 INITN 132 GND 133 DONE 134 GND 135 VCC 136 VCCAUX 137 PR9B 138 GND2 139 ...
Page 89
... Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number Pin Function Bank 169 PT21A 170 PT20B 171 PT20A 172 PT19B 173 PT19A 174 PT18B 175 PT18A 176 VCCIO1 177 VCCAUX 178 PT17B 179 GND0 180 PT17A 181 ...
Page 90
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA Ball Number Ball Function Bank GND GND7 7 D4 PL2A 7 D3 PL2B 7 C3 PL3A 7 C2 PL3B 7 B1 PL4A 7 C1 PL4B 7 E3 PL5A 7 E4 PL5B 7 F4 PL6A 7 F5 PL6B 7 G4 PL7A 7 G3 PL7B ...
Page 91
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function Bank K2 PL11A 6 K1 PL11B 6 L2 PL12A 6 L1 PL12B 6 M2 PL13A 6 M1 PL13B 6 N1 PL14A 6 GND GND6 6 N2 PL14B 6 M4 PL15A 6 M3 PL15B 6 P1 PL16A 6 R1 PL16B ...
Page 92
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function Bank GND GND5 5 T9 PB13B 5 P8 PB14A 5 N8 PB14B 5 R9 PB15A 5 R10 PB15B 5 P9 PB16A 5 N9 PB16B 5 T10 PB17A 5 GND GND5 5 T11 PB17B 5 T12 PB18A 4 T13 ...
Page 93
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function Bank N16 PR14A 3 N15 PR13B 3 M15 PR13A 3 M16 PR12B 3 L16 PR12A 3 K16 PR11B 3 J16 PR11A 3 L12 CFG2 3 L14 CFG1 3 L13 CFG0 3 K13 PROGRAMN 3 L15 CCLK 3 K15 ...
Page 94
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function Bank C16 PR4B 2 B16 PR4A 2 C15 PR3B 2 C14 PR3A 2 D14 PR2B 2 D13 PR2A 2 GND GND2 2 GND GND1 B13 NC - C13 NC - C12 PT25B D12 PT25A 1 A15 PT24B 1 B14 ...
Page 95
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function Bank D7 PT11B 0 C7 PT11A 0 A7 PT10B 0 A6 PT10A 0 E7 PT9B 0 GND GND0 0 E6 PT9A 0 D6 PT8B 0 C6 PT8A 0 B6 PT7B 0 B5 PT7A 0 A5 PT6B 0 A4 PT6A ...
Page 96
... Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Function Bank E5 VCC - E8 VCC - M12 VCC - M5 VCC - M9 VCC - B15 VCCAUX - R2 VCCAUX - F7 VCCIO0 0 F8 VCCIO0 0 F10 VCCIO1 1 F9 VCCIO1 1 G11 VCCIO2 2 H11 VCCIO2 2 J11 VCCIO3 3 K11 VCCIO3 3 L10 ...
Page 97
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank GND GND7 7 D4 PL2A 7 D3 PL2B 7 GND GND7 7 C3 PL12A 7 C2 PL12B 7 B1 PL13A 7 C1 PL13B 7 E3 PL14A 7 GND GND7 PL14B 7 F4 PL15A 7 F5 PL15B ...
Page 98
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank L3 TMS 6 L5 TDO 6 L4 VCCJ 6 K2 PL29A 6 K1 PL29B 6 L2 PL30A 6 L1 PL30B 6 M2 PL31A 6 M1 PL31B 6 N1 PL32A 6 GND GND6 PL32B 6 M4 PL33A 6 M3 ...
Page 99
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank N7 PB18B 5 R7 PB19A 5 R8 PB19B 5 M7 PB20A 5 M8 PB20B 5 T8 PB21A 5 GND GND5 5 T9 PB21B 5 P8 PB22A 5 N8 PB22B 5 R9 PB23A 5 R10 PB23B 5 P9 PB24A ...
Page 100
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank P14 PR35B 3 P15 PR35A 3 R15 PR34B 3 R16 PR34A 3 M13 PR33B 3 M14 PR33A 3 P16 PR32B 3 GND GND3 3 N16 PR32A 3 N15 PR31B 3 M15 PR31A 3 M16 PR30B 3 L16 ...
Page 101
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank G12 PR18A 2 G13 PR17B 2 F13 PR17A 2 F12 PR16B 2 E13 PR16A 2 D16 PR15B 2 D15 PR15A 2 F14 PR14B 2 GND GND2 2 E14 PR14A 2 C16 PR13B 2 B16 PR13A 2 C15 ...
Page 102
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank A10 PT25B 0 GND GND0 0 B10 PT25A 0 C9 PT24B 0 B9 PT24A 0 E9 PT23B 0 D9 PT23A 0 D8 PT22B 0 C8 PT22A 0 A9 PT21B 0 GND GND0 0 A8 PT21A 0 B8 ...
Page 103
... Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank G9 GND - H10 GND - H7 GND - H8 GND - H9 GND - J10 GND - J7 GND - J8 GND - J9 GND - K10 GND - K7 GND - K8 GND - K9 GND - T1 GND - T16 GND - E12 VCC - E5 VCC - E8 VCC - M12 VCC ...
Page 104
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function GND GND7 7 D4 PL2A 7 T VREF2_7 E4 PL2B 7 C VREF1_7 GND - - GND - - PL3A PL3B PL4A PL4B PL5A 7 T GND - - J3 PL5B PL6A 7 T LDQS6 ...
Page 105
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function M4 PL13A PL13B PL14A 6 T GND GND6 6 M2 PL14B PL15A 6 T LDQS15 M3 PL15B PL16A PL16B PL17A PL17B PL18A 6 T GND GND6 6 P2 ...
Page 106
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function GND GND5 AA3 NC - AB3 AA5 AA4 NC - GND - - AB4 PB2A PB2B PB3A PB3B PB4A PB4B PB5A 5 T GND - - Y9 PB5B PB6A 5 T BDQS6 ...
Page 107
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function V12 PB16B 5 C VREF1_5 AB10 PB17A 5 T PCLKT5_0 GND GND5 5 AB11 PB17B 5 C PCLKC5_0 Y12 PB18A 4 T WRITEN U11 PB18B 4 C CS1N ...
Page 108
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function W17 NC - AA20 NC - Y19 NC - Y18 NC - W18 NC - T17 NC - U17 NC - GND GND4 4 GND GND3 3 W20 PR27B 3 C VREF2_3 Y20 PR27A 3 T VREF1_3 AA21 PR26B ...
Page 109
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function N22 PR17A 3 T N19 PR16B 3 C N18 PR16A 3 T M21 PR15B 3 C L20 PR15A 3 T RDQS15 L21 PR14B 3 C GND GND3 ...
Page 110
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function C21 NC - C20 NC - F18 NC - E18 NC - B22 NC - B21 NC - E19 PR2B 2 C VREF1_2 D19 PR2A 2 T VREF2_2 GND GND2 2 GND GND1 1 G17 NC - F17 NC - D18 ...
Page 111
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function F14 PT23B 1 C D14 PT23A 1 T E13 PT22B 1 C G13 PT22A 1 T TDQS22 A12 PT21B 1 C GND GND1 1 B12 PT21A 1 T F13 ...
Page 112
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function GND - - A1 GND - A22 GND - AB1 GND - AB22 GND - H15 GND - H8 GND - J10 GND - J11 GND - J12 GND - J13 GND - J14 GND ...
Page 113
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function N13 GND - N14 GND - N9 GND - P10 GND - P11 GND - P12 GND - P13 GND - P14 GND - P9 GND - R15 GND - R8 GND - J16 VCC ...
Page 114
... Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Ball Dual Number Function Bank LVDS Function T11 VCCIO5 5 M7 VCCIO6 6 M8 VCCIO6 6 N8 VCCIO6 6 P8 VCCIO6 6 J8 VCCIO7 7 K8 VCCIO7 7 L7 VCCIO7 7 L8 VCCIO7 7 G15 VCCAUX - G16 ...
Page 115
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS GND GND7 7 D4 PL2A 7 E4 PL2B 7 GND - - C3 PL3A 7 B2 PL3B 7 E5 PL4A 7 F5 PL4B 7 D3 PL5A 7 C2 PL5B 7 GND - - F4 PL6A 7 G4 PL6B 7 E3 PL7A ...
Page 116
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS K2 PL21B 7 J1 PL22A 7 GND GND7 7 K1 PL22B 7 L3 XRES 6 L4 PL24A 6 L5 PL24B 6 L2 PL25A 6 L1 PL25B 6 M4 PL26A 6 M5 PL26B 6 M1 PL27A 6 GND ...
Page 117
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS U3 PL42A 6 V3 PL42B 6 U4 PL43A 6 V5 PL43B 6 W1 PL44A 6 GND GND6 6 W2 PL44B 6 Y1 PL45A 6 Y2 PL45B 6 AA1 PL46A 6 AA2 PL46B 6 W4 PL47A 6 V4 ...
Page 118
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS Y8 PB21A 5 GND GND5 5 Y9 PB21B 5 V9 PB22A 5 T9 PB22B 5 W10 PB23A 5 U10 PB23B 5 V10 PB24A 5 T10 PB24B 5 AA6 PB25A 5 GND GND5 5 AB5 PB25B 5 AA8 ...
Page 119
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS V14 PB40B 4 AA13 PB41A 4 GND GND4 4 AB13 PB41B 4 AA14 PB42A 4 Y14 PB42B 4 Y15 PB43A 4 W15 PB43B 4 V15 PB44A 4 T14 PB44B 4 AB14 PB45A 4 GND GND4 ...
Page 120
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS Y20 PR48A 3 GND - - GND - - AA21 PR47B 3 AB21 PR47A 3 W19 PR46B 3 V19 PR46A 3 Y21 PR45B 3 AA22 PR45A 3 V20 PR44B 3 GND GND3 3 U20 PR44A 3 W21 PR43B ...
Page 121
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS N19 PR29B 3 N18 PR29A 3 M21 PR28B 3 L20 PR28A 3 L21 PR27B 3 GND GND3 3 M20 PR27A 3 M18 PR26B 3 M19 PR26A 3 M22 PR25B 3 L22 PR25A 3 K22 PR24B ...
Page 122
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS G19 PR8B 2 G18 PR8A 2 F20 PR7B 2 F19 PR7A 2 E20 PR6B 2 D20 PR6A 2 C21 PR5B 2 GND - - C20 PR5A 2 F18 PR4B 2 E18 PR4A 2 B22 PR3B 2 B21 ...
Page 123
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS B15 PT46B 1 A16 PT46A 1 A15 PT45B 1 GND GND1 1 A14 PT45A 1 G14 PT44B 1 E15 PT44A 1 D15 PT43B 1 C15 PT43A 1 C14 PT42B 1 B14 PT42A 1 A13 PT41B ...
Page 124
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS A6 PT27A 0 B7 PT26B 0 B8 PT26A 0 A5 PT25B 0 GND GND0 0 B6 PT25A 0 G10 PT24B 0 E10 PT24A 0 F10 PT23B 0 D10 PT23A 0 G9 PT22B 0 E9 PT22A 0 C9 ...
Page 125
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS AB22 GND - H15 GND - H8 GND - J10 GND - J11 GND - J12 GND - J13 GND - J14 GND - J9 GND - K10 GND - K11 GND - K12 GND - K13 GND ...
Page 126
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS K17 VCC - K6 VCC - K7 VCC - L17 VCC - L6 VCC - M17 VCC - M6 VCC - N16 VCC - N17 VCC - N6 VCC - N7 VCC - P16 VCC - P7 VCC - G11 VCCIO0 0 H10 VCCIO0 0 H11 ...
Page 127
... Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS L8 VCCIO7 7 G15 VCCAUX - G16 VCCAUX - G7 VCCAUX - G8 VCCAUX - H16 VCCAUX - H7 VCCAUX - R16 VCCAUX - R7 VCCAUX - T15 VCCAUX - T16 VCCAUX - T7 VCCAUX - T8 VCCAUX - 1 J6 VCC - 1 J17 VCC - 1 P6 ...
Page 128
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA LFEC20/LFECP20 Ball Ball Number Function Bank LVDS GND GND7 7 E3 PL2A PL2B PL3A PL3B PL4A PL4B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A 7 T GND GND7 7 G4 PL9B PL11A PL11B ...
Page 129
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS K6 PL13B PL14A 7 T GND GND7 7 G1 PL14B PL15A PL15B PL16A PL16B PL17A PL17B PL18A 7 T GND GND7 7 L1 PL18B PL19A PL19B PL20A PL20B PL21A ...
Page 130
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS P5 PL32B PL33A PL33B PL34A PL34B PL35A 6 T GND GND6 6 T4 PL35B PL36A PL36B PL37A PL37B PL38A PL38B PL39A 6 T GND GND6 6 V2 PL39B TCK ...
Page 131
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS AA4 NC - AB3 NC - AC2 AC3 NC - AA5 NC - AB5 NC - AD3 NC - AD2 NC - AE1 NC - AD1 NC - AB4 PL48A 6 T AC4 PL48B 6 C GND GND6 6 GND GND5 5 AB6 PB2A 5 T AA6 ...
Page 132
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS AF4 PB13B 5 C AE5 PB14A 5 T AA9 PB14B 5 C AF5 PB15A 5 T Y10 PB15B 5 C AD6 PB16A 5 T AC10 PB16B 5 C AF6 PB17A 5 T GND ...
Page 133
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS AC13 PB32B 5 C AF14 PB33A 5 T GND GND5 5 AE14 PB33B 5 C AA13 PB34A 4 T AB13 PB34B 4 C AD14 PB35A 4 T AA14 PB35B 4 C AC14 ...
Page 134
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS AF22 PB51A 4 T AB17 PB51B 4 C AE22 PB52A 4 T AA18 PB52B 4 C AE19 PB53A 4 T GND GND4 4 AE20 PB53B 4 C AA19 PB54A 4 T Y18 ...
Page 135
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS Y19 NC - AA23 AA22 NC - AB23 NC - AB24 NC - Y21 NC - AA21 NC - Y23 NC - Y22 NC - AA24 Y24 NC - AC25 PR47B 3 C AC26 PR47A 3 T AB25 PR46B 3 C AA25 PR46A 3 T AB26 ...
Page 136
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS U21 PR36B 3 C T21 PR36A 3 T T25 PR35B 3 C GND GND3 3 T26 PR35A 3 T T22 PR34B 3 C T23 PR34A 3 T T24 PR33B 3 C R23 ...
Page 137
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS L24 PR17A 2 K25 PR16B 2 J25 PR16A 2 J26 PR15B 2 H26 PR15A 2 H25 PR14B 2 GND GND2 2 J24 PR14A 2 K21 PR13B 2 K22 PR13A 2 K20 PR12B 2 J20 PR12A ...
Page 138
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS E24 NC - D24 NC - E22 NC - F22 NC - E21 NC - D22 NC - E23 PR2B 2 D23 PR2A 2 GND GND2 2 GND GND1 1 G20 NC - F20 NC - D21 NC - C21 NC - C23 NC - C22 NC - B23 NC - C24 NC - D20 E19 ...
Page 139
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS A21 PT51A 1 T E17 PT50B 1 C B17 PT50A 1 T C17 PT49B 1 C GND GND1 1 D17 PT49A 1 T F17 PT48B 1 C E20 PT48A 1 T G17 ...
Page 140
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS D13 PT32B 0 C13 PT32A 0 A13 PT31B 0 B13 PT31A 0 F13 PT30B 0 F12 PT30A 0 A12 PT29B 0 GND GND0 0 B12 PT29A 0 A11 PT28B 0 B11 PT28A 0 D12 PT27B ...
Page 141
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS A5 PT13B 0 C GND GND0 0 A4 PT13A PT12B PT12A PT11B PT11A PT10B PT10A PT9B 0 C GND GND0 0 A2 PT9A PT8B PT8A PT7B PT7A PT6B PT6A ...
Page 142
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS M10 GND - M11 GND - M12 GND - M13 GND - M14 GND - M15 GND - M16 GND - M17 GND - N10 GND - N11 GND - N12 GND - N13 GND ...
Page 143
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS U12 GND - U13 GND - U14 GND - U15 GND - U16 GND - U17 GND - H10 VCC - H11 VCC - H16 VCC - H17 VCC - H18 VCC - H19 VCC ...
Page 144
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS J14 VCCIO1 1 J15 VCCIO1 1 J16 VCCIO1 1 J17 VCCIO1 1 K17 VCCIO2 2 K18 VCCIO2 2 L18 VCCIO2 2 M18 VCCIO2 2 N18 VCCIO2 2 N19 VCCIO2 2 P18 VCCIO3 3 P19 VCCIO3 ...
Page 145
... Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Ball Number Function Bank LVDS H7 VCCAUX - J19 VCCAUX - J8 VCCAUX - K7 VCCAUX - L20 VCCAUX - M20 VCCAUX - M7 VCCAUX - N20 VCCAUX - P20 VCCAUX - P7 VCCAUX - T20 VCCAUX - T7 VCCAUX - T8 VCCAUX - V19 VCCAUX - V7 VCCAUX - W20 VCCAUX ...
Page 146
... Lattice Semiconductor Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to fi ...
Page 147
... The markings appear as follows: © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 148
... LFEC3E-4Q208C 145 LFEC3E-5Q208C 145 LFEC3E-3T144C 97 LFEC3E-4T144C 97 LFEC3E-5T144C 97 LFEC3E-3T100C 67 LFEC3E-4T100C 67 LFEC3E-5T100C 67 Part Number I/Os LFEC6E-3F484C 224 LFEC6E-4F484C 224 LFEC6E-5F484C 224 LFEC6E-3F256C 195 LFEC6E-4F256C 195 LFEC6E-5F256C 195 LFEC6E-3Q208C 147 LFEC6E-4Q208C 147 LFEC6E-5Q208C 147 LFEC6E-3T144C 97 LFEC6E-4T144C 97 LFEC6E-5T144C 97 Part Number I/Os LFEC10E-3F484C 288 LFEC10E-4F484C 288 ...
Page 149
... Lattice Semiconductor Part Number I/Os LFEC10E-4F256C 195 LFEC10E-5F256C 195 LFEC10E-3Q208C 147 LFEC10E-4Q208C 147 LFEC10E-5Q208C 147 Part Number I/Os LFEC15E-3F484C 352 LFEC15E-4F484C 352 LFEC15E-5F484C 352 LFEC15E-3F256C 195 LFEC15E-4F256C 195 LFEC15E-5F256C 195 Part Number I/Os LFEC20E-3F672C 400 LFEC20E-4F672C 400 LFEC20E-5F672C 400 LFEC20E-3F484C 360 ...
Page 150
... Lattice Semiconductor Part Number I/Os LFECP6E-3F484C 224 LFECP6E-4F484C 224 LFECP6E-5F484C 224 LFECP6E-3F256C 195 LFECP6E-4F256C 195 LFECP6E-5F256C 195 LFECP6E-3Q208C 147 LFECP6E-4Q208C 147 LFECP6E-5Q208C 147 LFECP6E-3T144C 97 LFECP6E-4T144C 97 LFECP6E-5T144C 97 Part Number I/Os LFECP10E-3F484C 288 LFECP10E-4F484C 288 LFECP10E-5F484C 288 LFECP10E-3F256C 195 LFECP10E-4F256C 195 LFECP10E-5F256C 195 ...
Page 151
... LFEC3E-3T144I 97 LFEC3E-4T144I 97 LFEC3E-3T100I 67 LFEC3E-4T100I 67 Part Number I/Os LFEC6E-3F484I 224 LFEC6E-4F484I 224 LFEC6E-3F256I 195 LFEC6E-4F256I 195 LFEC6E-3Q208I 147 LFEC6E-4Q208I 147 LFEC6E-3T144I 97 LFEC6E-4T144I 97 Part Number I/Os LFEC10E-3F484I 288 LFEC10E-4F484I 288 LFEC10E-3F256I 195 LFEC10E-4F256I 195 LFEC10E-3 P208I 147 LFEC10E-4 P208I 147 LatticeECP Commercial (Continued) ...
Page 152
... Lattice Semiconductor Part Number I/Os LFEC15E-3F484I 352 LFEC15E-4F484I 352 LFEC15E-3F256I 195 LFEC15E-4F256I 195 Part Number I/Os LFEC20E-3F672I 400 LFEC20E-4F672I 400 LFEC20E-3F484I 360 LFEC20E-4F484I 360 Part Number I/Os LFEC33E-3F672I 496 LFEC33E-4F672I 496 LFEC33E-3F484I 360 LFEC33E-4F484I 360 Part Number I/Os LFECP6E-3F484I 224 LFECP6E-4F484I ...
Page 153
... Lattice Semiconductor Part Number I/Os LFECP20E-3F672I 400 LFECP20E-4F672I 400 LFECP20E-3F484I 360 LFECP20E-4F484I 360 Part Number I/Os LFECP33E-3F672I 496 LFECP33E-4F672I 496 LFECP33E-3F484I 360 LFECP33E-4F484I 360 LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Grade Package -3 fpBGA -4 fpBGA -3 fpBGA -4 fpBGA Grade Package -3 fpBGA -4 fpBGA ...
Page 154
... Part Number I/Os LFEC6E-3FN484C 224 LFEC6E-4FN484C 224 LFEC6E-5FN484C 224 LFEC6E-3FN256C 195 LFEC6E-4FN256C 195 LFEC6E-5FN256C 195 LFEC6E-3QN208C 147 LFEC6E-4QN208C 147 LFEC6E-5QN208C 147 LFEC6E-3TN144C 97 LFEC6E-4TN144C 97 LFEC6E-5TN144C 97 Part Number I/Os LFEC10E-3FN484C 288 LFEC10E-4FN484C 288 LFEC10E-5FN484C 288 LFEC10E-3FN256C 195 LatticeECP/EC Family Data Sheet LatticeEC Commercial ...
Page 155
... Lattice Semiconductor Part Number I/Os LFEC10E-4FN256C 195 LFEC10E-5FN256C 195 LFEC10E-3QN208C 147 LFEC10E-4QN208C 147 LFEC10E-5QN208C 147 Part Number I/Os LFEC15E-3FN484C 352 LFEC15E-4FN484C 352 LFEC15E-5FN484C 352 LFEC15E-3FN256C 195 LFEC15E-4FN256C 195 LFEC15E-5FN256C 195 Part Number I/Os LFEC20E-3FN672C 400 LFEC20E-4FN672C 400 LFEC20E-5FN672C 400 LFEC20E-3FN484C 360 ...
Page 156
... Lattice Semiconductor Part Number I/Os LFECP6E-3FN484C 224 LFECP6E-4FN484C 224 LFECP6E-5FN484C 224 LFECP6E-3FN256C 195 LFECP6E-4FN256C 195 LFECP6E-5FN256C 195 LFECP6E-3QN208C 147 LFECP6E-4QN208C 147 LFECP6E-5QN208C 147 LFECP6E-3TN144C 97 LFECP6E-4TN144C 97 LFECP6E-5TN144C 97 Part Number I/Os LFECP10E-3FN484C 288 LFECP10E-4FN484C 288 LFECP10E-5FN484C 288 LFECP10E-3FN256C 195 LFECP10E-4FN256C 195 LFECP10E-5FN256C 195 ...
Page 157
... LFEC3E-3TN144I 97 LFEC3E-4TN144I 97 LFEC3E-3TN100I 67 LFEC3E-4TN100I 67 Part Number I/Os LFEC6E-3FN484I 224 LFEC6E-4FN484I 224 LFEC6E-3FN256I 195 LFEC6E-4FN256I 195 LFEC6E-3QN208I 147 LFEC6E-4QN208I 147 LFEC6E-3TN144I 97 LFEC6E-4TN144I 97 Part Number I/Os LFEC10E-3FN484I 288 LFEC10E-4FN484I 288 LFEC10E-3FN256I 195 LFEC10E-4FN256I 195 LFEC10E-3QN208I 147 LFEC10E-4QN208I 147 LatticeECP Commercial (Continued) Grade ...
Page 158
... Lattice Semiconductor Part Number I/Os LFEC15E-3FN484I 352 LFEC15E-4FN484I 352 LFEC15E-3FN256I 195 LFEC15E-4FN256I 195 Part Number I/Os LFEC20E-3FN672I 400 LFEC20E-4FN672I 400 LFEC20E-3FN484I 400 LFEC20E-4FN484I 400 Part Number I/Os LFEC33E-3FN672I 496 LFEC33E-4FN672I 496 LFEC33E-3FN484I 360 LFEC33E-4FN484I 360 Part Number I/Os LFECP6E-3FN484I 224 LFECP6E-4FN484I ...
Page 159
... Lattice Semiconductor Part Number I/Os LFECP20E-3FN672I 400 LFECP20E-4FN672I 400 LFECP20E-3FN484I 400 LFECP20E-4FN484I 400 Part Number I/Os LFECP33E-3FN672I 496 LFECP33E-4FN672I 496 LFECP33E-3FN484I 360 LFECP33E-4FN484I 360 LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Grade Package -3 Lead-Free fpBGA -4 Lead-Free fpBGA -3 Lead-Free fpBGA -4 Lead-Free fpBGA ...
Page 160
... PCI: ww.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 161
... Ordering Information © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 162
... Lattice Semiconductor Date Version December 2004 01.4 Architecture Pinout Information Ordering Information Supplemental Information April 2005 01.5 Architecture DC & Switching Characteristics Pinout Information May 2005 01.6 Introduction Architecture DC & Switching Characteristics Pinout Information Ordering Information Section Updated Hot Socketing Recommended Power Up Sequence section. ...
Page 163
... Lattice Semiconductor Date Version September 2005 02.0 Architecture DC & Switching Characteristics Pinout Information November 2005 02.1 DC & Switching Characteristics Ordering Information March 2006 02.2 DC & Switching Characteristics January 2007 02.3 Architecture February 2007 02.4 Architecture May 2007 02.5 Architecture November 2007 02.6 DC & ...