AD6643BCPZ-200 Analog Devices Inc, AD6643BCPZ-200 Datasheet
AD6643BCPZ-200
Specifications of AD6643BCPZ-200
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AD6643BCPZ-200 Summary of contents
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FEATURES Performance with NSR enabled SNR: 76.1 dBFS MHz band to 90 MHz at 185 MSPS SNR: 73.6 dBFS MHz band to 90 MHz at 185 MSPS Performance with NSR disabled SNR: 66.5 dBFS ...
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AD6643 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 ADC DC Specifications................................................................. 4 ADC AC Specifications ................................................................. 5 Digital Specifications ..................................................................... ...
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When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. ...
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AD6643 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing ...
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ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE-RATIO (SNR) NSR Disabled f ...
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AD6643 1 Parameter TWO TONE SFDR f = 184.12 MHz, 187.12 MHz (−7 dBFS CROSSTALK FULL POWER BANDWIDTH 3 4 NOISE BANDWIDTH 1 For a complete set of definitions, see the AN-835 2 Crosstalk is measured at 100 ...
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Parameter Input Current Level High Low Input Resistance Input Capacitance 1 LOGIC INPUTS (SDIO) Input Voltage Level High Low Input Current Level High Low Input Resistance Input Capacitance 2 LOGIC INPUTS (OEB, PDWN) Input Voltage Level High Low Input Current ...
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AD6643 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode 2 2 CLK Pulse Width High Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT ...
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Timing Diagrams VIN CLK+ CLK– DCO– DCO+ PARALLEL INTERLEAVED D0 (LSB CHANNEL A AND . CHANNEL B D11 (MSB) CHANNEL MULTIPLEXED 0/D0± (EVEN/ODD) MODE (LSB CHANNEL A . D9/D10± (MSB) CHANNEL MULTIPLEXED 0/D0± (EVEN/ODD) MODE (LSB) ...
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AD6643 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INDICATOR D0– (LSB) D0+ (LSB) NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE Table 8. Pin Function Descriptions for ...
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AD6643 Pin No. Mnemonic 27 D4+ 26 D4− 30 D5+ 29 D5− 32 D6+ 31 D6− 34 D7+ 33 D7− 36 D8+ 35 D8− 39 D9+ 38 D9− 41 D10+ (MSB) 40 D10− (MSB) 43 OR+ 42 OR− 25 DCO+ ...
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INDICATOR CLK+ CLK– SYNC DRVDD B 0/D0– (LSB) B 0/D0+ (LSB) B D1–/D2– B D1+/D2+ B D3–/D4– B D3+/D4+ NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM ...
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AD6643 Pin No. Mnemonic 16 B D3+/D4 D5−/D6− D5+/D6 D7−/D8− D7+/D8 D9−/D10− (MSB D9+/D10+ (MSB 0/D0− (LSB 0/D0+ (LSB D1−/D2− ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 200 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample 25°C, unless otherwise noted 200MSPS 30.1MHz @ ...
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AD6643 120 100 SNR (dBFS) 80 SFDR (dBFS SNR (dBc –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (A 100 95 SFDR (dBc ...
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SNR, CHANNEL B SFDR, CHANNEL B 75 SNR, CHANNEL A SFDR, CHANNEL 100 110 120 130 140 150 160 SAMPLE RATE (MSPS) Figure 18. Single ...
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AD6643 EQUIVALENT CIRCUITS AVDD VIN Figure 20. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 21. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 22. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ ...
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THEORY OF OPERATION The AD6643 has two analog input channels and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port( filtered, and optionally decimated, digital signal. ADC ...
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AD6643 decoupling capacitor close to the VCM pin to minimize series resistance and inductance between the device and this capacitor. Differential Input Configurations Optimum performance is achieved by driving the AD6643 in a differential input configuration. For baseband applications, the ...
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AD8376 NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. VOLTAGE REFERENCE A stable and accurate voltage reference is ...
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AD6643 0.1µF CLOCK INPUT AD95xx 100Ω PECL DRIVER 0.1µF CLOCK INPUT 50kΩ 50kΩ Figure 36. Differential LVDS Sample Clock (Up to 625 MHz) Input Clock Divider The AD6643 contains an input clock divider with the ability to divide the input ...
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Asserting the PDWN pin low returns the AD6643 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed ...
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AD6643 NOISE SHAPING REQUANTIZER (NSR) The AD6643 features a noise shaping requantizer (NSR) to allow higher than 11-bit SNR to be maintained in a subset of the Nyquist band. The harmonic performance of the receiver is unaffected by the NSR ...
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BW MODE (>60 MHZ AT 184.32 MSPS) The second bandwidth mode offers excellent noise performance over 33% of the ADC sample rate (66% of the Nyquist band) and can be centered by setting the NSR mode bits in the ...
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AD6643 CHANNEL/CHIP SYNCHRONIZATION The AD6643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized ...
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SERIAL PORT INTERFACE (SPI) The AD6643 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...
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AD6643 SPI ACCESSIBLE FEATURES Table 13 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI (available at ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel ...
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AD6643 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration ...
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Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x0D Test mode User test Open (local) mode control 0 = continuous/ repeat pattern 1 = single pattern then zeros 0x0E BIST enable Open Open (local) 0x10 Offset adjust Open Open ...
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AD6643 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x1D User Test Pattern 3 LSB (global) 0x1E User Test Pattern 3 MSB (global) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST ...
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NSR Control (Register 0x3C) Bits[7:4]—Reserved Bits[3:1]—NSR Mode Bits[3:1] determine the bandwidth mode of the NSR. When Bits[3:1] are set to 000, the NSR is configured for a 22% BW mode that provides enhanced SNR performance over 22% of the sample ...
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AD6643 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD6643 recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD6643BCPZ-200 −40°C to +85°C AD6643BCPZRL7-200 −40°C to +85°C AD6643-200EBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ ...
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AD6643 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09638-0-4/11(0) Rev Page ...