AD6649BCPZ Analog Devices Inc, AD6649BCPZ Datasheet
AD6649BCPZ
Specifications of AD6649BCPZ
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AD6649BCPZ Summary of contents
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FEATURES SNR = 73.0 dBFS MHz bandwidth at 185 MHz A and 245.76 MSPS IN SFDR = 85 dBc at 185 MHz A and 250 MSPS IN Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 ...
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AD6649 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 ADC DC Specifications................................................................. 4 ADC AC Specifications ................................................................. 5 Digital Specifications ..................................................................... ...
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ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled ...
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AD6649 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY ...
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ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 2. 2 Parameter 3 SIGNAL-TO-NOISE RATIO (SNR ...
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AD6649 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input ...
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Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS FDA and FDB High Level Output Voltage μ 0 Low Level Output Voltage μA OL LVDS Data ...
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AD6649 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-3 Through Divide-by-8 Modes, ...
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TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to the rising edge of CLK setup time SSYNC t SYNC to the rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data ...
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AD6649 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INDICATOR D0– (LSB) D0+ (LSB) DRVDD NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR ...
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AD6649 Pin No. Mnemonic 15 D3− 18 D4+ 17 D4− 21 D5+ 20 D5− 23 D6+ 22 D6− 27 D7+ 26 D7− 30 D8+ 29 D8− 32 D9+ 31 D9− 34 D10+ 33 D10− 36 D11+ 35 D11− 39 D12+ ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample 25°C, fixed-frequency NCO, 95 MHz BW FIR filter, unless ...
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AD6649 120 SFDR (dBFS) 100 SNR (dBFS SFDR (dBc) 20 SNR (dBc) 0 INPUT AMPLITUDE (dBFS) Figure 11. AD6649 Single-Tone SNR/SFDR vs. Input Amplitude (A with f = 90.1 MHz IN 100 95 SFDR (dBc ...
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SFDR CHANNEL A (dBc) 85 SFDR CHANNEL B (dBc) SNR CHANNEL A (dBFS) SNR CHANNEL B (dBFS SAMPLE RATE (MSPS) Figure 17. AD6649 Single-Tone SNR/SFDR vs. Sample Rate ( 90.1 MHz IN ...
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AD6649 EQUIVALENT CIRCUITS AVDD VIN Figure 19. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 20. Equivalent Clock Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 21. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ ...
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THEORY OF OPERATION The AD6649 has two analog input channels, two filter channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port( filtered and optionally decimated ...
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AD6649 Differential Input Configurations Optimum performance is achieved while driving the AD6649 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, ADA4938-2, and differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode ...
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VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD6649. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT ...
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AD6649 Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock ...
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DIGITAL OUTPUTS The AD6649 output drivers can be configured for either ANSI LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format ...
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AD6649 DIGITAL PROCESSING The AD6649 includes a digital processing section that provides filtering. This digital processing section includes a numerically controlled oscillator (NCO), a selectable FIR filter (high perfor- mance or low latency), and a second coarse NCO (f value) ...
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NUMERICALLY CONTROLLED OSCILLATOR (NCO) FREQUENCY TRANSLATION This processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (NCO). The NCO is always enabled. This NCO block accepts a real input from the ADC stage and outputs ...
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AD6649 FIR FILTERS The two FIR filters that can be used are either a 47-tap, high performance, fixed-coefficient FIR filter or a 21-tap, low latency, fixed-coefficient FIR filter. These filters are useful in providing alias protection at the device output. ...
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FILTER RESPONSE (MHz) Figure 43. High Performance FIR Filter Pass-Band Response at 245.76 MSPS (Tunable-Frequency NCO, 100 MHz FIR Filter) 0 –0.1 –0.2 –0.3 ...
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AD6649 ADC OVERRANGE AND GAIN CONTROL In receiver applications desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides delayed information on the state of the analog ...
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DC CORRECTION Because the dc offset of the ADC may be significantly larger than the signal being measured correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be ...
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AD6649 CHANNEL/CHIP SYNCHRONIZATION The AD6649 has a SYNC input that allows the user flexible syn- chronization options for synchronizing the internal blocks. The SYNC feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider, NCO, FIR ...
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SERIAL PORT INTERFACE (SPI) The AD6649 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...
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AD6649 SPI ACCESSIBLE FEATURES Table 14 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD6649 ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel ...
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AD6649 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 15 are not currently supported for this device. Table 15. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0D Test mode User test Open (local) mode control 0 = con- tinuous/ repeat pattern 1 = single pattern, then 0s 0x0E BIST enable Open Open (local) 0x10 Open Open Offset ...
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AD6649 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x3A Sync control Open Open (global) ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x51 NCO control Reserved NCO32 to (local NCO S sync enable 0x52 NCO Frequency 3 (local) 0x53 NCO Frequency 2 (local) 0x54 NCO Frequency 1 (local) 0x55 NCO Frequency ...
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AD6649 MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application to High Speed ADCs via SPI. Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the ...
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Bit 2—9-bit Output Mode Enable If this bit is set, the NCOs and filters are bypassed and the part outputs nine bits of data. These nine bits are presented on the nine MSBs of the output bus (that is, Bit ...
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AD6649 SYNC Pin Control (Register 0x59) Bits[7:2]—Reserved Bit 1—SYNC Pin Sensitivity If Bit 1 is set the SYNC input responds to a level. If this bit is set low, the SYNC input responds to the edge (rising ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD6649 recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD6649BCPZ −40°C to +85°C AD6649BCPZRL7 −40°C to +85°C AD6649EBZ RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX ...