AD9643BCPZ-210 Analog Devices Inc, AD9643BCPZ-210 Datasheet
AD9643BCPZ-210
Specifications of AD9643BCPZ-210
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AD9643BCPZ-210 Summary of contents
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FEATURES SNR = 70.6 dBFS at 185 MHz A and 250 MSPS IN SFDR = 85 dBc at 185 MHz A and 250 MSPS IN −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A 250 MSPS Total power consumption: ...
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AD9643 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 ...
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SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, unless otherwise noted. Table 1. Parameter Temperature RESOLUTION ...
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AD9643 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2. 1 Parameter Temperature SIGNAL-TO-NOISE-RATIO (SNR ...
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Parameter Temperature 2 CROSSTALK Full 3 FULL POWER BANDWIDTH 25°C 4 NOISE BANDWIDTH 25°C 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 ...
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AD9643 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic ...
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Parameter DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 Pull-up. 2 Pull-down. Temp Min ...
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AD9643 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 ...
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TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to the rising edge of CLK setup time SSYNC t SYNC to the rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data ...
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AD9643 Timing Diagrams VIN CLK+ CLK– DCO– DCO+ PARALLEL INTERLEAVED D0± (LSB CHANNEL A AND . CHANNEL B D13± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL A . D12±/D13± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND PDWN ...
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AD9643 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INDICATOR (LSB) D0– (LSB) D0+ Table 8. Pin Function Descriptions for Interleaved Parallel LVDS Mode Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, 59, 60, 63, 64 ...
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Pin No. Mnemonic 17 D4− 21 D5+ 20 D5− 23 D6+ 22 D6− 27 D7+ 26 D7− 30 D8+ 29 D8− 32 D9+ 31 D9− 34 D10+ 33 D10− 36 D11+ 35 D11− 39 D12+ 38 D12− 41 D13+ (MSB) ...
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AD9643 INDICATOR (LSB) B D0–/D1– (LSB) B D0+/D1+ DRVDD B D2–/D3– B D2+/D3+ B D4–/D5– B D4+/D5+ B D6–/D7– B D6+/D7+ Figure 5. LFCSP Channel Multiplexed (Even/Odd) LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions for Channel Multiplexed ...
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Pin No. Mnemonic 14 B D4+/D5 D6−/D7− D6+/D7 D8−/D9− D8+/D9 D10−/D11− D10+/D11 D12−/D13− (MSB D12+/D13+ (MSB D0−/D1− (LSB D0+/D1+ (LSB) ...
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AD9643 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample 25°C, unless otherwise noted 170MSPS 90.1MHz ...
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SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –78.5 –67.0 –55.5 –44.0 INPUT AMPLITUDE (dBFS) Figure 12. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 184.12 187.12 MHz, f ...
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AD9643 0 210MSPS 185.1MHz @ –1dBFS –20 SNR = 70.3dB (71.3dBFS) SFDR = 86dBc –40 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 18. AD9643-210 Single-Tone FFT with f ...
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SFDR = 88dBc (95dBFS) –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 24. AD9643-210 Two-Tone FFT with f IN1 f = 210 MSPS ...
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AD9643 0 250MSPS 305.1MHz @ –1dBFS –20 SNR = 68.6dB (71.6dBFS) SFDR = 83dBc –40 –60 THIRD HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 30. AD9643-250 Single-Tone FFT with f 120 ...
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SFDR = 87dBc (94dBFS) –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 36. AD9643-250 Two-Tone FFT with f = 184.12, f ...
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AD9643 EQUIVALENT CIRCUITS AVDD VIN Figure 39. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 40. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 41. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ ...
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THEORY OF OPERATION The AD9643 has two analog input channels and two digital output channels. The intermediate frequency (IF) signal passes through several stages before appearing at the output port(s). The dual ADC design can be used for diversity reception ...
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AD9643 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the set with the VCM pin of the AD9643 (see Figure 47), and the driver can be configured in a Sallen-Key filter ...
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VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9643. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT ...
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AD9643 Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock ...
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DIGITAL OUTPUTS The AD9643 output drivers can be configured for either ANSI LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format ...
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AD9643 CHANNEL/CHIP SYNCHRONIZATION The AD9643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The SYNC feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized ...
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SERIAL PORT INTERFACE (SPI) The AD9643 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...
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AD9643 SPI ACCESSIBLE FEATURES Table 13 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9643 ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel ...
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AD9643 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0D Test mode User test Open (local) mode control 0 = con- tinuous/ repeat pattern 1 = single pattern, then 0s 0x0E BIST enable Open Open (local) 0x10 Open Open Offset ...
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AD9643 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x3A Sync control Open Open (global) ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system level design and layout of the AD9643 recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9643BCPZ-170 −40°C to +85°C AD9643BCPZ-210 −40°C to +85°C AD9643BCPZ-250 −40°C to +85°C AD9643BCPZRL7-170 −40°C to +85°C AD9643BCPZRL7-210 −40°C to +85°C AD9643BCPZRL7-250 −40°C to +85°C AD9643-170EBZ − ...