LFXP2-40E-6FN672C | |
|---|---|
| Manufacturer Part Number | LFXP2-40E-6FN672C |
| Description | IC DSP 40KLUTS 540I/O 672FPBGA |
| Manufacturer | Lattice |
| LFXP2-40E-6FN672C datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of LFXP2-40E-6FN672C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | * | Number Of Labs/clbs | * |
| Total Ram Bits | 906240 | Number Of I /o | 540 |
| Number Of Gates | - | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | * | Operating Temperature | 0°C ~ 85°C |
| Package / Case | * | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 220-1129 | ||
PrevNext
Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8.
Figure 2-8. Edge Clock Sources
CLKOP
PLL
GPLL
CLKOS
Input
From Routing
Clock
Input
Clock
Input
From Routing
CLKOP
PLL
GPLL
CLKOS
Input
Sources for left edge clocks
Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.
Clock Input
Clock Input
From
From
Routing
Routing
Sources for top
edge clocks
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Sources for
bottom edge
From
From
Routing
Routing
Clock Input
Clock Input
2-11
Architecture
LatticeXP2 Family Data Sheet
CLKOP
PLL
CLKOS GPLL
Input
From Routing
Clock
Input
Clock
Input
From Routing
CLKOP
PLL
CLKOS GPLL
Input
Sources for right edge clocks
clocks
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