LFXP2-40E-6FN672C | |
|---|---|
| Manufacturer Part Number | LFXP2-40E-6FN672C |
| Description | IC DSP 40KLUTS 540I/O 672FPBGA |
| Manufacturer | Lattice |
| LFXP2-40E-6FN672C datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Shipping terms
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Specifications of LFXP2-40E-6FN672C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | * | Number Of Labs/clbs | * |
| Total Ram Bits | 906240 | Number Of I /o | 540 |
| Number Of Gates | - | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | * | Operating Temperature | 0°C ~ 85°C |
| Package / Case | * | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 220-1129 | ||
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PrevNext
February 2008
Features
flexiFLASH™ Architecture
• Instant-on
• Infinitely reconfigurable
• Single chip
• FlashBAK™ technology
• Serial TAG memory
• Design security
Live Update Technology
• TransFR™ technology
• Secure updates with 128 bit AES encryption
• Dual-boot with external SPI
sysDSP™ Block
• Three to eight blocks for high performance
Multiply and Accumulate
• 12 to 32 18x18 multipliers
• Each block supports one 36x36 multiplier or four
18x18 or eight 9x9 multipliers
Embedded and Distributed Memory
• Up to 885 Kbits sysMEM™ EBR
• Up to 83 Kbits Distributed RAM
sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting
Table 1-1. LatticeXP2 Family Selection Guide
Device
LUTs (K)
Distributed RAM (KBits)
EBR SRAM (KBits)
EBR SRAM Blocks
sysDSP Blocks
18 x 18 Multipliers
V
Voltage
CC
GPLL
Max Available I/O
Packages and I/O Combinations
132-Ball csBGA (8 x 8 mm)
144-Pin TQFP (20 x 20 mm)
208-Pin PQFP (28 x 28 mm)
256-Ball ftBGA (17 x17 mm)
484-Ball fpBGA (23 x 23 mm)
672-Ball fpBGA (27 x 27 mm)
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LatticeXP2 Family Data Sheet
Flexible I/O Buffer
• sysIO™ buffer supports:
– LVCMOS 33/25/18/15/12; LVTTL
– SSTL 33/25/18 class I, II
– HSTL15 class I; HSTL18 class I, II
– PCI
– LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
Pre-engineered Source Synchronous
Interfaces
• DDR / DDR2 interfaces up to 200 MHz
• 7:1 LVDS interfaces support display applications
• XGMII
Density And Package Options
• 5k to 40k LUT4s, 86 to 540 I/Os
• csBGA, TQFP , PQFP , ftBGA and fpBGA packages
• Density migration supported
Flexible Device Configuration
• SPI (master and slave) Boot Flash Interface
• Dual Boot Image supported
• Soft Error Detect (SED) macro embedded
System Level Support
• IEEE 1149.1 and IEEE 1532 Compliant
• On-chip oscillator for initialization & general use
• Devices operate with 1.2V power supply
XP2-5
XP2-8
XP2-17
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1-1
Introduction
Data Sheet DS1009
XP2-30
XP2-40
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Introduction_01.2
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