LFXP2-40E-6FN672C | |
|---|---|
| Manufacturer Part Number | LFXP2-40E-6FN672C |
| Description | IC DSP 40KLUTS 540I/O 672FPBGA |
| Manufacturer | Lattice |
| LFXP2-40E-6FN672C datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of LFXP2-40E-6FN672C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | * | Number Of Labs/clbs | * |
| Total Ram Bits | 906240 | Number Of I /o | 540 |
| Number Of Gates | - | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | * | Operating Temperature | 0°C ~ 85°C |
| Package / Case | * | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 220-1129 | ||
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PrevNext
Lattice Semiconductor
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The
overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.
Figure 2-21. MAC sysDSP
Serial Register B in
Multiplicand
n
Multiplier
n
n
Input Data
Register B
n
Signed A
Signed B
Addn
Accumsload
SROB
Serial Register A in
m
m
m
Multiplier
Input Data
m
Register A
x
n
Pipeline
n
Register
Input
Pipeline
To Accumulator
Register
Register
Input
Pipeline
To Accumulator
Register
Register
Input
Pipeline
To Accumulator
Register
Register
Input
Pipeline
To Accumulator
Register
Register
SROA
2-21
LatticeXP2 Family Data Sheet
Preload
Accumulator
m+n+16
(default)
m+n
m+n+16
(default)
(default)
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Architecture
Output
Overflow
signal
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