LFXP2-40E-6FN672C | |
|---|---|
| Manufacturer Part Number | LFXP2-40E-6FN672C |
| Description | IC DSP 40KLUTS 540I/O 672FPBGA |
| Manufacturer | Lattice |
| LFXP2-40E-6FN672C datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of LFXP2-40E-6FN672C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | * | Number Of Labs/clbs | * |
| Total Ram Bits | 906240 | Number Of I /o | 540 |
| Number Of Gates | - | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | * | Operating Temperature | 0°C ~ 85°C |
| Package / Case | * | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 220-1129 | ||
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PrevNext
Lattice Semiconductor
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-26. Input Register Block
DI
(From sysIO
Buffer)
Fixed Delay
0
Dynamic Delay
1
DEL [3:0]
From
Routing
Delayed
0
DQS
1
CLK0 (of PIO A)
DDRCLKPOL
CLKA
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
DI
(From sysIO
Buffer)
Fixed Delay
0
Dynamic Delay
1
DEL [3:0]
From
Routing
Delayed
0
DQS
1
CLK0 (of PIO B)
DDRCLKPOL
CLKB
1. Shared with output register
2. Selected PIO.
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The blocks on the PIOs on the left, right and bottom contain registers for SDR operation that
are combined with an additional latch for DDR operation. Figure 2-27 shows the diagram of the Output Register
Block for PIOs.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. At the next
clock cycle the registered OPOS0 is latched. A multiplexer running off the same clock cycle selects the correct reg-
ister to feed the output (D0).
By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox
function can be implemented, to take four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-27
SDR & Sync
DDR Registers
Registers
0
D0
1
Q
D
D-Type
D1
D2
Q
D
Q
D
D-Type
D-Type
DDRSRC
SDR & Sync
DDR Registers
Registers
0
D0
0
1
D
Q
1
D-Type
0
D1
D
Q
D
Q
D2
1
D-Type
D-Type
Gearbox Configuration Bit
2-28
Architecture
LatticeXP2 Family Data Sheet
2
INCK
To DQS Delay Block
INDD
Clock Transfer Registers
IPOS0A
Q
D
D
Q
QPOS0A
D-Type
1
/LATCH
D-Type
IPOS1A
Q
D
D
QPOS1A
Q
D-Type
1
D-Type
/LATCH
To
Routing
2
INCK
To DQS Delay Block
INDD
Clock Transfer Registers
IPOS0B
Q
D
Q
D
QPOS0B
D-Type
1
D-Type
/LATCH
IPOS1B
Q
Q
D
D
QPOS1B
D-Type
1
D-Type
/LATCH
To
Routing
Note: Simplified version does not
show CE and SET/RESET details
2
2
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