LFXP2-40E-6FN672C | |
|---|---|
| Manufacturer Part Number | LFXP2-40E-6FN672C |
| Description | IC DSP 40KLUTS 540I/O 672FPBGA |
| Manufacturer | Lattice |
| LFXP2-40E-6FN672C datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of LFXP2-40E-6FN672C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | * | Number Of Labs/clbs | * |
| Total Ram Bits | 906240 | Number Of I /o | 540 |
| Number Of Gates | - | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | * | Operating Temperature | 0°C ~ 85°C |
| Package / Case | * | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 220-1129 | ||
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PrevNext
Lattice Semiconductor
shows the diagram using this gearbox function. For more information on this topic, see TN1138,
Speed I/O
Interface.
Figure 2-27. Output and Tristate Block
TD
Tristate Logic
ONEG1
OPOS1
Q
ONEG0
D
*
D-Type
OPOS0
Q
D
*
D-Type
CLKA
Clock Transfer
Registers
ECLK1
ECLK2
CLK1
(CLKA)
DQSXFER
TD
Tristate Logic
ONEG1
OPOS1
Q
ONEG0
D
D-Type*
OPOS0
D
Q
D-Type*
CLKB
Clock Transfer
Registers
ECLK1
ECLK2
CLK1
(CLKB)
DQSXFER
* Shared with input register
0
0
1
1
0
Q
D
0
1
Latch
1
0
0
1
1
D
Q
Latch
0
0
1
1
Note: Simplified version does not show CE and SET/RESET details
2-29
Architecture
LatticeXP2 Family Data Sheet
LatticeXP2 High
D
Q
0
D-Type
1
/LATCH
0
1
0
1
D
Q
D
Q
D-Type
Latch
DDR Output
D
Q
Registers
D-Type
/LATCH
0
1
0
1
D
Q
D
Q
D-Type
Latch
Programmable
Control
Output Logic
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
Q
D
0
D-Type
1
/LATCH
0
1
0
1
Q
Q
D
D
D-Type
Latch
Q
D
D-Type
DDR Output
/LATCH
Registers
0
1
0
1
D
Q
D
Q
Latch
D-Type
Programmable
Control
Output Logic
TO
DO
TO
DO
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