LFXP2-40E-6FN672C | |
|---|---|
| Manufacturer Part Number | LFXP2-40E-6FN672C |
| Description | IC DSP 40KLUTS 540I/O 672FPBGA |
| Manufacturer | Lattice |
| LFXP2-40E-6FN672C datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of LFXP2-40E-6FN672C | |||
|---|---|---|---|
| Number Of Logic Elements/cells | * | Number Of Labs/clbs | * |
| Total Ram Bits | 906240 | Number Of I /o | 540 |
| Number Of Gates | - | Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | * | Operating Temperature | 0°C ~ 85°C |
| Package / Case | * | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 220-1129 | ||
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PrevNext
Lattice Semiconductor
LatticeXP2 Internal Switching Characteristics
Parameter
Description
Asynchronous reset time for PFU
t
RST_PIO
Logic
t
Dynamic Delay Step Size
DEL
EBR Timing
Clock (Read) to Output from
t
CO_EBR
Address or Data
Clock (Write) to Output from EBR
t
COO_EBR
Output Register
Setup Data to EBR Memory
t
SUDATA_EBR
(Write Clk)
Hold Data to EBR Memory (Write
t
HDATA_EBR
Clk)
Setup Address to EBR Memory
t
SUADDR_EBR
(Write Clk)
Hold Address to EBR Memory
t
HADDR_EBR
(Write Clk)
Setup Write/Read Enable to EBR
t
SUWREN_EBR
Memory (Write/Read Clk)
Hold Write/Read Enable to EBR
t
HWREN_EBR
Memory (Write/Read Clk)
Clock Enable Setup Time to EBR
t
SUCE_EBR
Output Register (Read Clk)
Clock Enable Hold Time to EBR
t
HCE_EBR
Output Register (Read Clk)
Reset To Output Delay Time from
t
EBR Output Register (Asynchro-
RSTO_EBR
nous)
Byte Enable Set-Up Time to EBR
t
SUBE_EBR
Output Register
Byte Enable Hold Time to EBR
t
Output Register Dynamic Delay
HBE_EBR
on Each PIO
Asynchronous reset recovery
t
RSTREC_EBR
time for EBR
t
Asynchronous reset time for EBR
RST_EBR
PLL Parameters
After RSTK De-assert, Recovery
t
Time Before Next Clock Edge
RSTKREC_PLL
Can Toggle K-divider Counter
After RST De-assert, Recovery
Time Before Next Clock Edge
t
Can Toggle M-divider Counter
RSTREC_PLL
(Applies to M-Divider Portion of
2
RST Only
)
DSP Block Timing
t
Input Register Setup Time
SUI_DSP
t
Input Register Hold Time
HI_DSP
t
Pipeline Register Setup Time
SUP_DSP
Over Recommended Operating Conditions
-7
Min.
Max.
—
0.386
0.035
0.035
—
2.774
—
0.360
-0.167
—
0.194
—
-0.117
—
0.157
—
-0.135
—
0.158
—
0.144
—
-0.097
—
—
1.156
-0.117
—
0.157
—
0.233
—
—
1.156
1.000
—
1.000
—
0.135
—
0.021
—
2.505
—
3-20
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
1
(Continued)
-6
-5
Min.
Max.
Min.
Max.
—
0.419
—
0.452
0.035
0.035
0.035
0.035
—
3.142
—
3.510
—
0.408
—
0.456
-0.198
—
-0.229
—
0.231
—
0.267
—
-0.137
—
-0.157
—
0.182
—
0.207
—
-0.159
—
-0.182
—
0.186
—
0.214
—
0.160
—
0.176
—
-0.113
—
-0.129
—
—
1.341
—
1.526
-0.137
—
-0.157
—
0.182
—
0.207
—
0.291
—
0.347
—
—
1.341
—
1.526
1.000
—
1.000
—
1.000
—
1.000
—
0.151
—
0.166
—
-0.006
—
-0.031
—
2.784
—
3.064
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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