LFXP2-40E-6FN672C

Manufacturer Part NumberLFXP2-40E-6FN672C
DescriptionIC DSP 40KLUTS 540I/O 672FPBGA
ManufacturerLattice
LFXP2-40E-6FN672C datasheets

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Specifications of LFXP2-40E-6FN672C

Number Of Logic Elements/cells*Number Of Labs/clbs*
Total Ram Bits906240Number Of I /o540
Number Of Gates-Voltage - Supply1.14 V ~ 1.26 V
Mounting Type*Operating Temperature0°C ~ 85°C
Package / Case*Lead Free Status / Rohs StatusLead free / RoHS Compliant
Other names220-1129  
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June 2008
Signal Descriptions
Signal Name
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
GSRN
NC
GND
V
CC
V
CCAUX
V
CCPLL
V
CCIOx
V
, V
REF1_x
REF2_x
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_V
CCPLL
[LOC][num]_GPLL[T, C]_IN_A
[LOC][num]_GPLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
[LOC]DQS[num]
Test and Programming (Dedicated Pins)
TMS
TCK
TDI
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LatticeXP2 Family Data Sheet
I/O
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
I/O
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
I
Global RESET signal (active low). Any I/O pin can be GSRN.
—
No connect.
—
Ground. Dedicated pins.
—
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. This dedicated pin powers all the differential and
—
referenced input buffers.
—
PLL supply pins. csBGA, PQFP and TQFP packages only.
—
Dedicated power supply pins for I/O bank x.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
—
assigned as V
inputs. When not used, they may be used as I/O pins.
REF
—
Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center.
General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row
I
from center, T = true and C = complement, index A,B,C...at each side.
Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from
I
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
I
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
I
function number. Any pad can be configured to be output.
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
I
enabled during configuration.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
I
enabled.
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
I
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
4-1
Pinout Information
Data Sheet DS1009
Description
Pinout Information_01.5

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