LC4064ZE-5MN64C Lattice, LC4064ZE-5MN64C Datasheet
LC4064ZE-5MN64C
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LC4064ZE-5MN64C Summary of contents
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... Pb-free only. © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Introduction The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam- ily is based on Lattice’s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family’ ...
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... Lattice Semiconductor The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs support the standards com- patible with the power supply provided to the bank. Support for a variety of standards helps designers implement designs in mixed voltage environments ...
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... Lattice Semiconductor Figure 3. AND Array In[0] In[34] In[35] Note: Indicates programmable fuse. Enhanced Logic Allocator Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product terms ...
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... Lattice Semiconductor Product Term Allocator The product term allocator assigns product terms from a cluster to either logic or control applications as required by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ- ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated with the cluster ...
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... Lattice Semiconductor Table 4. Product Term Expansion Capability Expansion Chains Chain-0 Chain-1 Chain-2 Chain-3 Every time the super cluster allocator is used, there is an incremental delay of t tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus- ter is steered to M (n+4), then M (n) is ground) ...
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... Lattice Semiconductor • Block CLK2 • Block CLK3 • PT Clock • PT Clock Inverted • Shared PT Clock • Ground Clock Enable Multiplexer Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol- lowing four sources: • ...
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... Lattice Semiconductor Output Routing Pool (ORP) The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block. This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This allows the OE product term to follow the macrocell output switched between I/O cells ...
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... Lattice Semiconductor Table 6. GLB/MC/ORP Combinations for ispMACH 4128ZE GLB/MC [GLB] [MC 0] M0, M1, M2, M3, M4, M5, M6, M7 [GLB] [MC 1] M1, M2, M3, M4, M5, M6, M7, M8 [GLB] [MC 2] M2, M3, M4, M5, M6, M7, M8, M9 [GLB] [MC 3] M4, M5, M6, M7, M8, M9, M10, M11 [GLB] [MC 4] M5, M6, M7, M8, M9, M10, M11, M12 ...
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... Lattice Semiconductor Figure 8. I/O Cell GOE 0 GOE 1 GOE 2 GOE 3 From ORP VCC From ORP To Macrocell To GRP Block Input Enable (BIE) (From Block PT) Each output supports a variety of output standards dependent on the V also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde- pendent of the V supplied to its I/O bank ...
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... Lattice Semiconductor Figure 9. Power Guard All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external sources using one of the user I/O or input pins. ...
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... Lattice Semiconductor The number of BIE inputs, thus the number of Power Guard “Blocks” that can exist in a device, depends on the device size. Table 8 shows the number of BIE signals available in the ispMACH 4000ZE family. The number of I/Os available in each block is shown in the Ordering Information section of this data sheet. ...
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... Lattice Semiconductor The block-level each GLB is also tied to Block Input Enable (BIE) of that block. Hence, for a 256-macro- cell device (with 16 blocks), each block's BIE signal is driven by block-level OE PT from each block. Figure 11. Global OE Generation for All Devices Except ispMACH 4032ZE Shared PTOE ...
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... Lattice Semiconductor Figure 13. On-Chip Oscillator and Timer Table 11. On-Chip Oscillator and Timer Signal Names Input or Out- Signal Name put OSCOUT Output TIMEROUT Output TIMERRES Input DYNOSCDIS Input OSCTIMER has two outputs, OSCOUT and TIMEROUT. The outputs feed into the Global Routing Pool (GRP). ...
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... Lattice Semiconductor Some Simple Use Scenarios The following diagrams show a few simple examples that omit optional signals for the OSCTIMER block oscillator giving 5MHz nominal clock B. An oscillator that can be disabled with an external signal (5MHz nominal clock oscillator giving approximately 5 Hz nominal clock (TIMER_DIV = 2 D ...
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... I/O cells. This quick config- uration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system ...
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... Lattice Semiconductor mated test equipment. This equipment can then be used to program ispMACH 4000ZE devices during the testing of a circuit board. User Electronic Signature The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the 2 device, stored in E CMOS memory. The ispMACH 4000ZE device contains 32 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes ...
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... Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management 3. All voltages referenced to GND. ...
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... Lattice Semiconductor I/O Recommended Operating Conditions Standard LVTTL LVCMOS 3.3 Extended LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 PCI 3.3 1. Typical values for V DC Electrical Characteristics Symbol Parameter Input Leakage Current Input High Leakage Current IH I I/O Weak Pull-up Resistor Current ...
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... Lattice Semiconductor Supply Current Symbol Parameter ispMACH 4032ZE ICC Operating Power Supply Current ICC Standby Power Supply Current ispMACH 4064ZE ICC Operating Power Supply Current ICC Standby Power Supply Current ispMACH 4128ZE ICC Operating Power Supply Current ICC Standby Power Supply Current ...
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... Lattice Semiconductor I/O DC Electrical Characteristics V Standard Min (V) LVTTL -0.3 LVCMOS 3.3 -0.3 LVCMOS 2.5 -0.3 LVCMOS 1.8 -0.3 0. LVCMOS 1.5 -0.3 0. PCI 3.3 -0.3 0 The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA ...
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... Family Data Sheet LC4064ZE All Devices - Min. Max. Min. Max. Min. — 4.7 — 5.8 — 2.5 — 2.9 — 4.5 2.7 — ...
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... The Lattice design tools report the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device ...
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... GOi Propagation Delay through Transparent Latch to Output/ t PDLi Feedback MUX Asynchronous Reset or Set to Output/Feedback MUX t SRi Delay Over Recommended Operating Conditions Description 24 ispMACH 4000ZE Family Data Sheet LC4032ZE LC4064ZE -4 -4 Min. Max. Min. Max. — 0.85 — 0.90 — 1.60 — ...
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... IN GCLK_IN GOE GCLK_IN GOE GCLK_IN GOE DIS BUF 25 ispMACH 4000ZE Family Data Sheet LC4032ZE LC4064ZE -4 -4 Min. Max. Min. Max. — 2.00 — 1.70 — 1.20 — 1.30 — 1.40 — 1.50 — 1.10 — 1.85 — 1.20 — 1.90 — ...
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... DIS BUF DIS BUF DIS BUF DIS BUF BUF 26 ispMACH 4000ZE Family Data Sheet LC4032ZE LC4064ZE -4 -4 Min. Max. Min. Max. — 0.20 — 0.20 — 0.00 — 0.00 — 0.10 — 0.10 — 0.20 — 0.20 — 0.20 — 0.20 — ...
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... Lattice Semiconductor ispMACH 4000ZE Internal Timing Parameters (Cont.) Parameter In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN t Output Disable Time DIS t Input Power Guard Setup Time ...
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... Lattice Semiconductor ispMACH 4000ZE Internal Timing Parameters (Cont.) Parameter t Asynchronous Reset or Set Recovery Delay SRR Control Delays t GLB PT Clock Delay BCLK t Macrocell PT Clock Delay PTCLK t Block PT Set/Reset Delay BSR t Macrocell PT Set/Reset Delay PTSR t Power Guard Block Input Enable Delay BIE t Macrocell PT OE Delay ...
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... Lattice Semiconductor ispMACH 4000ZE Internal Timing Parameters (Cont.) Parameter LVCMOS15_out Output Configured as 1.5V Buffer LVCMOS18_out Output Configured as 1.8V Buffer LVCMOS25_out Output Configured as 2.5V Buffer LVCMOS33_out Output Configured as 3.3V Buffer Output Configured as PCI Compati- PCI_out ble Buffer Output Configured for Slow Slew ...
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... Lattice Semiconductor Boundary Scan Waveforms and Timing Specifications Symbol t TCK [BSCAN test] clock cycle BTCP t TCK [BSCAN test] pulse width high BTCH t TCK [BSCAN test] pulse width low BTCL t TCK [BSCAN test] setup time BTSU t TCK [BSCAN test] hold time BTH ...
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... Lattice Semiconductor Power Consumption Power Estimation Coefficients Device ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE 1. For further information about the use of these coefficients, refer to TN1187, mation in ispMACH 4000ZE ispMACH 4000ZE Typical I vs. Frequency 4256ZE 50 40 4128ZE 100 150 200 Frequency (MHz) ...
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... Lattice Semiconductor Switching Test Conditions Figure 17 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 13. Figure 17. Output Test Load, LVTTL and LVCMOS Standards Table 13. Test Fixture Required Components Test Condition LVCMOS I/O, (L -> ...
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... Lattice Semiconductor Signal Descriptions Signal Names TMS TCK TDI TDO GOE0/IO, GOE1/IO GND CLK0/I, CLK1/I, CLK2/I, CLK3 CCO0 CCO1 yzz 1. In some packages, certain I/Os are only available for use as inputs. See the Logic Signal Connections tables for details. ORP Reference Table ...
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... Lattice Semiconductor ispMACH 4000ZE Power Supply and NC Connections Signal 48 TQFP VCC 12, 36 VCCO0 6 VCCO (Bank 0) VCCO1 30 VCCO (Bank 1) GND 13, 37 GND (Bank 0) 5 GND (Bank — 1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown ...
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... Lattice Semiconductor ispMACH 4000ZE Power Supply and NC Connections Signal 132 ucBGA VCC M1, M7, A12, B5 VCCO0 B1, H4, L2, J5, A4 VCCO (Bank 0) VCCO1 K9, L12, F12, D9, C7 VCCO (Bank 1) GND E5, E8, H5, H8 GND (Bank 0) E2, H2, M4, B7, B3 GND (Bank 1) L7, J9, H12, E9 — 1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown ...
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... Lattice Semiconductor ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP Pin Number ispMACH 4000ZE Family Data Sheet ispMACH 4032ZE Bank Number GLB/MC/Pad - GND (Bank 0) 0 VCCO (Bank CLK1/I 1 CLK2 GND (Bank 1) 1 VCCO (Bank B15/GOE1 1 CLK3/I 36 ispMACH 4064ZE GLB/MC/Pad TDI TDI ...
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... Lattice Semiconductor ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP (Cont.) Pin Number ispMACH 4000ZE Family Data Sheet ispMACH 4032ZE Bank Number GLB/MC/Pad 0 CLK0/I 0 A0/GOE0 ispMACH 4064ZE GLB/MC/Pad CLK0/I A0/GOE0 ...
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... Lattice Semiconductor ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA Ball Number GND GND GND GND ispMACH 4000ZE Family Data Sheet ispMACH 4032ZE Bank Number GLB/MC/Pad - GND (Bank VCCO (Bank CLK1/I 1 CLK2 GND (Bank VCCO (Bank ispMACH 4064ZE GLB/MC/Pad TDI TDI ...
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... Lattice Semiconductor ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA (Cont.) Ball Number GND GND All bonded grounds are connected to the following two balls, D4 and E5. ispMACH 4000ZE Family Data Sheet ispMACH 4032ZE Bank Number GLB/MC/Pad B15/GOE1 1 CLK3/I 0 CLK0/I 0 A0/GOE0 ispMACH 4064ZE ...
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... Lattice Semiconductor ispMACH 4064ZE Logic Signal Connections: 64 ucBGA Ball Number GND GND GND GND ispMACH 4000ZE Family Data Sheet Bank Number - GLB/MC/Pad TDI A8 A10 A11 GND (Bank 0) A12 VCCO (Bank 0) B15 B14 B13 B12 B11 B10 B9 B8 TCK VCC GND B6 B5 ...
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... Lattice Semiconductor ispMACH 4064ZE Logic Signal Connections: 64 ucBGA (Cont.) Ball Number GND GND All bonded grounds are connected to the following two balls, D4 and E5. ispMACH 4000ZE Family Data Sheet Bank Number GLB/MC/Pad D13 D12 D11 D10 D9 D8 TDO VCC GND GND (Bank 1) ...
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... LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad GND TDI A8 A9 A10 A11 GND (Bank 0) GND (Bank 0) A12 A13 A14 A15 I VCCO (Bank 0) VCCO (Bank 0) B15 B14 B13 B12 GND (Bank 0) GND (Bank 0) B11 B10 TCK VCC GND GND (Bank 0) GND (Bank 0) VCCO (Bank 0) ...
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... LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad VCCO (Bank 1) VCCO (Bank 1) GND (Bank 1) GND (Bank GND TMS C8 C9 C10 C11 GND (Bank 1) GND (Bank 1) C12 C13 C14 C15 I VCCO (Bank 1) VCCO (Bank 1) D15 D14 D13 D12 GND (Bank 1) GND (Bank 1) D11 D10 D9 D8 ...
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... This pin is input only. LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad VCCO (Bank 1) VCCO (Bank D0/GOE1 H0/GOE1 CLK3/I CLK0/I VCC A0/GOE0 VCCO (Bank 0) VCCO (Bank 0) GND (Bank 0) GND (Bank ispMACH 4000ZE Family Data Sheet LC4256ZE GLB/MC/Pad VCCO (Bank 1) H6 P12 H4 P10 H2 P2/GOE1 CLK3/I ...
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... Lattice Semiconductor ispMACH 4128ZE Logic Signal Connections: 132 ucBGA Ball Number GND GND ispMACH 4000ZE Family Data Sheet Bank Number - - GLB/MC/Pad GND TDI VCCO (Bank GND (Bank B10 B12 B13 B14 VCCO (Bank 0) C14 C13 C12 C10 C9 C8 GND (Bank 0) C6 ...
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... Lattice Semiconductor ispMACH 4128ZE Logic Signal Connections: 132 ucBGA (Cont.) Ball Number L10 K10 M10 L11 K12 M11 GND* M12 L12 K11 J10 H9 J12 J11 H10 H12 G9 H11 F9 G12 G11 G10 F12 F10 F11 E11 E10 ispMACH 4000ZE Family Data Sheet ...
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... Lattice Semiconductor ispMACH 4128ZE Logic Signal Connections: 132 ucBGA (Cont.) Ball Number D10 E12 E9 D12 D11 C12 C10 C11 B11 D9 B12 A12 GND* A10 A11 B10 ispMACH 4000ZE Family Data Sheet Bank Number GLB/MC/Pad G9 G8 GND (Bank VCCO (Bank 1) TDO VCC ...
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... Lattice Semiconductor ispMACH 4128ZE Logic Signal Connections: 132 ucBGA (Cont.) Ball Number A2 * All bonded core grounds are connected to the following four balls, E5, E8, H5 and H8. ispMACH 4000ZE Family Data Sheet Bank Number 0 48 GLB/MC/Pad A14 ...
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... K2 L3* 0 LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad GND TDI NC Ball VCCO (Bank 0) NC Ball NC Ball A8 A9 A10 A11 GND (Bank 0) GND (Bank 0) NC Ball NC Ball NC Ball A12 A13 A14 A15 I VCCO (Bank 0) VCCO (Bank 0) B15 B14 B13 B12 NC Ball NC Ball NC Ball GND (Bank 0) ...
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... M10 1 L10 M11 M12 - H9 1 L12 1 L11 1 K10 1 K12 1 J10 1 K11 LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad GND (Bank 0) GND (Bank 0) VCCO (Bank 0) VCCO (Bank 0) NC Ball NC Ball CLK1/I NC Ball GND (Bank 1) CLK2/I VCC Ball NC Ball VCCO (Bank 1) VCCO (Bank 1) GND (Bank 1) GND (Bank 1) ...
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... F7 - A12 1 C10 1 B10 1 A11 A10 LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad NC Ball NC Ball NC Ball C12 C13 C14 C15 I VCCO (Bank 1) VCCO (Bank 1) D15 D14 D13 D12 NC Ball NC Ball NC Ball GND (Bank 1) GND (Bank 1) D11 D10 Ball NC Ball VCCO (Bank 1) TDO VCC GND ...
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... This pin is input only for the LC4064ZE. LC4064ZE LC4128ZE GLB/MC/Pad GLB/MC/Pad D0/GOE1 H0/GOE1 CLK3/I NC Ball GND (Bank 0) CLK0/I VCC A0/GOE0 A0/GOE0 Ball NC Ball VCCO (Bank 0) VCCO (Bank 0) GND (Bank 0) GND (Bank Ball NC Ball NC Ball 52 ispMACH 4000ZE Family Data Sheet LC4256ZE GLB/MC/Pad ...
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... Lattice Semiconductor ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP Pin Number ispMACH 4000ZE Family Data Sheet LC4128ZE Bank Number GLB/MC/Pad - - 0 VCCO (Bank GND (Bank GND (Bank 0) 0 VCCO (Bank GND (Bank VCCO (Bank LC4256ZE GLB/MC/Pad GND GND TDI ...
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... Lattice Semiconductor ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.) Pin Number ispMACH 4000ZE Family Data Sheet LC4128ZE Bank Number GLB/MC/Pad GND (Bank 0) 0 VCCO (Bank CLK1/I 1 GND (Bank 1) 1 CLK2 VCCO (Bank 1) 1 GND (Bank VCCO (Bank 1) ...
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... Lattice Semiconductor ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.) Pin Number 89 92 100 101 102 103 104 105 106 107 108 109 110* 111 112 113 114 115 116 117* 118 119 120 121 122 123 124 125 ...
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... Lattice Semiconductor ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.) Pin Number 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144* * This pin is input only for the LC4256ZE. ispMACH 4000ZE Family Data Sheet ...
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... Lattice Semiconductor Part Number Description LC XXXX XX – XXX X XX Device Family Device Number 4032 = 32 Macrocells 4064 = 64 Macrocells 4128 = 128 Macrocells 4256 = 256 Macrocells Power ZE = Zero Power, Enhanced Speed 4 = 4.4ns (4032ZE Only 4.7ns (4064ZE Only 5.8ns (All Devices 7.5ns (All Devices) ispMACH 4000ZE Family Speed Grade Offering ...
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... Lead-Free Packaging Device Part Number LC4032ZE-4TN48C LC4032ZE-5TN48C LC4032ZE-7TN48C LC4032ZE LC4032ZE-4MN64C LC4032ZE-5MN64C LC4032ZE-7MN64C LC4064ZE-4TN48C LC4064ZE-5TN48C LC4064ZE-7TN48C LC4064ZE-4TN100C LC4064ZE-5TN100C LC4064ZE-7TN100C LC4064ZE-4MN64C LC4064ZE LC4064ZE-5MN64C LC4064ZE-7MN64C LC4064ZE-4UMN64C LC4064ZE-5UMN64C LC4064ZE-7UMN64C LC4064ZE-4MN144C LC4064ZE-5MN144C LC4064ZE-7MN144C LC4128ZE-5TN100C LC4128ZE-7TN100C LC4128ZE-5TN144C LC4128ZE-7TN144C LC4128ZE LC4128ZE-5UMN132C LC4128ZE-7UMN132C LC4128ZE-5MN144C LC4128ZE-7MN144C ispMACH 4000ZE Family Data Sheet ...
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... Device Part Number LC4032ZE-5TN48I LC4032ZE-7TN48I LC4032ZE LC4032ZE-5MN64I LC4032ZE-7MN64I LC4064ZE-5TN48I LC4064ZE-7TN48I LC4064ZE-5TN100I LC4064ZE-7TN100I LC4064ZE-5MN64I LC4064ZE LC4064ZE-7MN64I LC4064ZE-5UMN64I LC4064ZE-7UMN64I LC4064ZE-5MN144I LC4064ZE-7MN144I LC4128ZE-7TN100I LC4128ZE-7UMN132I LC4128ZE LC4128ZE-7TN144I LC4128ZE-7MN144I LC4256ZE-7TN100I LC4256ZE LC4256ZE-7TN144I LC4256ZE-7MN144I For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 4000ZE family: • ...
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... Lattice Semiconductor Revision History Date Version April 2008 01.0 Initial release. July 2008 01.1 Updated Features bullets. Updated typical Hysteresis voltage. Updated Power Guard for Dedicated Inputs section. Updated DC Electrical Characteristics table. Updated Supply Current table. Updated I/O DC Electrical Characteristics table and note 2. ...