LPC1778FBD208,551 NXP Semiconductors, LPC1778FBD208,551 Datasheet - Page 93

• Manufacturer Part Number: LPC1778FBD208,551
• Description: MCU ARM 512K FLASH 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1778FBD208,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 165
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Processor Series: LPC177x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: SSP, I2S, USB, JTAG, Serial, UART, I2C, SD/MMC
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 100 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6690

NXP Semiconductors
LPC178X_7X
Objective data sheet
Fig 27. Differential data-to-EOP transition skew and EOP width
t
PERIOD
differential
data lines
11.10 Ethernet
Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76.
Table 26.
T
[1]
[2]
Symbol Parameter
RMII mode
f
d
t
t
MII mode
f
d
t
t
f
d
t
t
clk
su
h
clk
su
h
clk
su
h
amb
clk
clk
clk
Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
=

40
n × t
differential data to
clock frequency
clock duty cycle
set-up time
hold time
clock frequency
clock duty cycle
set-up time
hold time
clock frequency
clock duty cycle
set-up time
hold time
crossover point

SE0/EOP skew
Dynamic characteristics: Ethernet
C to 85
PERIOD
All information provided in this document is subject to legal disclaimers.
+ t

FDEOP
C, V
DD(REG)(3V3)
Rev. 2 — 27 May 2011
Conditions
for ENET_RX_CLK
for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
for ENET_TX_CLK
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
for ENET_RX_CLK
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
= 3.0 V to 3.6 V. Values guaranteed by design.
crossover point
extended
32-bit ARM Cortex-M3 microcontroller
source EOP width: t
receiver EOP width: t
[1]
[1]
[1][2]
[1][2]
[1]
[1]
[1][2]
[1][2]
[1]
[1]
[1][2]
[1][2]
LPC178x/7x
Min
-
50
4
2
-
50
4
2
-
50
4
2
© NXP B.V. 2011. All rights reserved.
FEOPT
002aab561
EOPR1
Max
50
50
-
-
25
50
-
-
25
50
-
-
, t
EOPR2
93 of 117
Unit
MHz
%
ns
ns
MHz
%
ns
ns
MHz
%
ns
ns