LPC1788FET208,551 NXP Semiconductors, LPC1788FET208,551 Datasheet - Page 49

• Manufacturer Part Number: LPC1788FET208,551
• Description: MCU ARM 512K FLASH 208-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1788FET208,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 165
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-TFBGA
• Processor Series: LPC178x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: SSP, I2S, USB, JTAG, Serial, UART, I2C, SD/MMC
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 100 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6691

NXP Semiconductors
LPC178X_7X
Objective data sheet
7.14.1 Features
7.14 Ethernet
Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
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Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
100 Base-FX, and 100 Base-T4.
pressure.
Redundancy Check (CRC) for transmit.
receive filters or a magic frame detection filter.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 27 May 2011
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
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