LPC1788FET208,551 NXP Semiconductors, LPC1788FET208,551 Datasheet - Page 92

MCU ARM 512K FLASH 208-TFBGA

LPC1788FET208,551

Manufacturer Part Number
LPC1788FET208,551
Description
MCU ARM 512K FLASH 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets

Specifications of LPC1788FET208,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
165
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-TFBGA
Processor Series
LPC178x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
SSP, I2S, USB, JTAG, Serial, UART, I2C, SD/MMC
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
165
Number Of Timers
4
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
100 mA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6691

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1788FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 25.
C
[1]
LPC178X_7X
Objective data sheet
Symbol
t
t
t
V
t
t
t
t
t
t
r
f
FRFM
FEOPT
FDEOP
JR1
JR2
EOPR1
EOPR2
L
CRS
= 50 pF; R
Characterized but not implemented as production test. Guaranteed by design.
Dynamic characteristics of USB pins (full-speed)
pu
= 1.5 k
11.9 USB
Parameter
rise time
fall time
differential rise and fall time
matching
output signal crossover voltage
source SE0 interval of EOP
source jitter for differential transition
to SE0 transition
receiver jitter to next transition
receiver jitter for paired transitions
EOP width at receiver
EOP width at receiver
on D+ to V
Fig 26. I
I2S_RX_SCK
I2S_RX_SDA
I2S_RX_WS
2
DD(3V3)
S-bus timing (receive)
All information provided in this document is subject to legal disclaimers.
; 3.0 V
V
Rev. 2 — 27 May 2011
DD(3V3)
t
WH
Conditions
10 % to 90 %
10 % to 90 %
see
see
10 % to 90 %
must reject as
EOP; see
Figure 27
must accept as
EOP; see
Figure 27
t
r
/ t
Figure 27
Figure 27
f
T
cy(clk)
3.6 V.
t
WL
t
su(D)
t
su(D)
[1]
[1]
32-bit ARM Cortex-M3 microcontroller
Min
7.7
-
160
2
18.5
9
40
82
8.5
1.3
t
t
su(D)
h(D)
Typ
-
-
-
-
-
-
-
-
-
-
t
f
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
Max
13.8
13.7
109
2.0
175
+5
+18.5
+9
-
-
t
r
002aag203
92 of 117
Unit
ns
ns
%
V
ns
ns
ns
ns
ns
ns

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