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STM32F215RET6
STM32F215RET6 | |
|---|---|
| Manufacturer Part Number | STM32F215RET6 |
| Description | MCU ARM 512KB FLASH 64LQFP |
| Manufacturer | STMicroelectronics |
| Series | STM32 |
| STM32F215RET6 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of STM32F215RET6 | |||
|---|---|---|---|
| Core Processor | ARM® Cortex-M3™ | Core Size | 32-Bit |
| Speed | 120MHz | Connectivity | CAN, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG |
| Peripherals | Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT | Number Of I /o | 51 |
| Program Memory Size | 512KB (512K x 8) | Program Memory Type | FLASH |
| Eeprom Size | - | Ram Size | 132K x 8 |
| Voltage - Supply (vcc/vdd) | 1.8 V ~ 3.6 V | Data Converters | A/D 16x12b; D/A 2x12b |
| Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 64-LFQFP | Lead Free Status / Rohs Status | Lead free / RoHS Compliant |
| Other names | 497-11178 | ||
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STM32F215xx, STM32F217xx
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms
FSMC_NE
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_NADV
Table 69.
Asynchronous multiplexed PSRAM/NOR read timings
Symbol
t
FSMC_NE low time
w(NE)
t
FSMC_NEx low to FSMC_NOE low
v(NOE_NE)
t
FSMC_NOE low time
w(NOE)
t
FSMC_NOE high to FSMC_NE high hold time
h(NE_NOE)
t
FSMC_NEx low to FSMC_A valid
v(A_NE)
t
FSMC_NEx low to FSMC_NADV low
v(NADV_NE)
t
FSMC_NADV low time
w(NADV)
FSMC_AD (address) valid hold time after
t
h(AD_NADV)
FSMC_NADV high
t
Address hold time after FSMC_NOE high
h(A_NOE)
t
FSMC_BL hold time after FSMC_NOE high
h(BL_NOE)
t
FSMC_NEx low to FSMC_BL valid
v(BL_NE)
t
Data to FSMC_NEx high setup time
su(Data_NE)
t
Data to FSMC_NOE high setup time
su(Data_NOE)
t
Data hold time after FSMC_NEx high
h(Data_NE)
t
Data hold time after FSMC_NOE high
h(Data_NOE)
1. C
= 15 pF.
L
2. Preliminary values.
t
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
v(A_NE)
Address
t
v(BL_NE)
NBL
t
su(Data_NE)
t
t
v(A_NE)
su(Data_NOE)
Address
Data
t
t
v(NADV_NE)
h(AD_NADV)
t
w(NADV)
Parameter
7T
3T
4T
–1
3
T
HCLK
T
HCLK
T
HCLK
0
2T
2T
0
0
Doc ID 17050 Rev 4
Electrical characteristics
t
h(NE_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
h(Data_NE)
t
h(Data_NOE)
ai14892b
(1)(2)
Min
Max
Unit
– 2
7T
+ 2
ns
HCLK
HCLK
– 0.5 3T
+ 1.5
ns
HCLK
HCLK
– 1
4T
+ 2
ns
HCLK
HCLK
ns
0
ns
5
ns
–1.5
T
+ 1.5
ns
HCLK
ns
ns
ns
0
ns
+ 24
ns
HCLK
+ 25
ns
HCLK
ns
ns
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