STM32F215RET6

Manufacturer Part NumberSTM32F215RET6
DescriptionMCU ARM 512KB FLASH 64LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F215RET6 datasheets

Availability: In stock

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of STM32F215RET6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed120MHzConnectivityCAN, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDTNumber Of I /o51
Program Memory Size512KB (512K x 8)Program Memory TypeFLASH
Eeprom Size-Ram Size132K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 VData ConvertersA/D 16x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-LFQFPLead Free Status / Rohs StatusLead free / RoHS Compliant
Other names497-11178  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Page 71
72
Page 72
73
Page 73
74
Page 74
75
Page 75
76
Page 76
77
Page 77
78
Page 78
79
Page 79
80
Page 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
Page 80/158

Download datasheet (3Mb)Embed
PrevNext
Electrical characteristics
Table 29.
Main PLL characteristics (continued)
Symbol
Parameter
t
PLL lock time
LOCK
Cycle-to-cycle jitter
Period Jitter
(3)
Jitter
Main clock output (MCO) for
Ethernet
Main clock output (MCO) for
OTG FS
Bit Time CAN jitter
(4)
I
PLL power consumption on VDD
DD(PLL)
PLL power consumption on
(4)
I
DDA(PLL)
VDDA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Table 30.
PLLI2S (audio PLL) characteristics
Symbol
Parameter
f
PLLI2S input clock
PLLI2S_IN
f
PLLI2S multiplier output clock
PLLI2S_OUT
f
PLLI2S VCO output
VCO_OUT
t
PLLI2S lock time
LOCK
80/158
Conditions
VCO freq = 192 MHz
VCO freq = 432 MHz
System clock
120 MHz
Cycle to cycle at 50 MHz
on 1000 samples
Cycle to cycle at 25 MHz
on 1000 samples
Cycle to cycle at 1 MHz
on 1000 samples
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
(1)
Conditions
(2)
VCO freq = 192 MHz
VCO freq = 432 MHz
Doc ID 17050 Rev 4
STM32F215xx, STM32F217xx
Min
Typ
Max
75
-
200
100
-
300
RMS
-
25
-
peak
±150
to
-
-
peak
RMS
-
15
-
peak
±200
to
-
-
peak
-
32
-
-
40
-
-
330
-
0.15
0.40
-
0.45
0.75
0.30
0.40
-
0.55
0.85
Min
Typ
Max
(3)
0.95
1
2.1
-
-
216
192
-
432
75
-
200
100
-
300
Unit
µs
ps
mA
mA
Unit
(3)
MHz
MHz
MHz
µs