STM32F215RET6

Manufacturer Part NumberSTM32F215RET6
DescriptionMCU ARM 512KB FLASH 64LQFP
ManufacturerSTMicroelectronics
SeriesSTM32
STM32F215RET6 datasheets

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Specifications of STM32F215RET6

Core ProcessorARM® Cortex-M3™Core Size32-Bit
Speed120MHzConnectivityCAN, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDTNumber Of I /o51
Program Memory Size512KB (512K x 8)Program Memory TypeFLASH
Eeprom Size-Ram Size132K x 8
Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 VData ConvertersA/D 16x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-LFQFPLead Free Status / Rohs StatusLead free / RoHS Compliant
Other names497-11178  
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Page 96/158

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Electrical characteristics
2
Table 47.
I
C characteristics
Symbol
t
SCL clock low time
w(SCLL)
t
SCL clock high time
w(SCLH)
t
SDA setup time
su(SDA)
t
SDA data hold time
h(SDA)
t
r(SDA)
SDA and SCL rise time
t
r(SCL)
t
f(SDA)
SDA and SCL fall time
t
f(SCL)
t
Start condition hold time
h(STA)
Repeated Start condition
t
su(STA)
setup time
t
Stop condition setup time
su(STO)
Stop to Start condition time
t
w(STO:STA)
(bus free)
Capacitive load for each bus
C
b
line
1. Guaranteed by design, not tested in production.
2. f
must be higher than 4 MHz to achieve the fast mode I
PCLK1
achieve the maximum fast mode I
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
96/158
Standard mode I
Parameter
Min
4.7
4.0
250
(3)
0
-
-
4.0
4.7
4.0
4.7
-
2
C frequency.
Doc ID 17050 Rev 4
STM32F215xx, STM32F217xx
2
(1)
2
(1)(2)
C
Fast mode I
C
Max
Min
Max
-
1.3
-
-
0.6
-
-
100
-
(4)
(3)
-
0
900
1000
20 + 0.1C
300
b
300
-
300
-
0.6
-
-
0.6
-
-
0.6
-
-
1.3
-
400
-
400
2
C frequency. It must be higher than 4 MHz to
Unit
µs
ns
µs
μs
μs
pF