IC PROGRAM DELAY 3.3V ECL 32LQFP

MC100EP196FAG

Manufacturer Part NumberMC100EP196FAG
DescriptionIC PROGRAM DELAY 3.3V ECL 32LQFP
ManufacturerON Semiconductor
Series100EP
TypeProgrammable Delay Chip
MC100EP196FAG datasheet
 


Specifications of MC100EP196FAG

InputECL, LVCMOS, LVTTLOutputECL
Frequency - Max1.2GHzVoltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case32-LQFPFrequency-max1.2GHz
FunctionActive Programmable Delay LineSupply Voltage (min)+/- 3 V
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (max)+/- 3.6 V
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesMC100EP196FAGOS
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
Page 1/18

Download datasheet (191Kb)Embed
Next
MC100EP196
3.3V ECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V
to V
to fine tune the output delay from 0 to 60 ps.
CC
EE
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
LEN allows a transparent LOAD mode of real time delay values by
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
current values present against any subsequent changes in D[10:0]. The
approximate delay values for varying tap numbers correlating to D0 (LSB)
through D9 (MSB) are shown in Table 5.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between V
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
operation is available in PECL mode only. For LVCMOS input levels,
leave V
and V
open. For ECL operation, short V
CF
EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V
and leave open V
CF
EF
to V
pin can be accomplished by placing a 2.2 kW resistor between
CF
V
and V
for 3.3 V power supply.
CF
EE
The V
pin, an internally generated voltage supply, is available to
BB
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
and V
CC
to 0.5 mA. When not used, V
should be left open.
BB
The 100 Series contains temperature compensation.
Maximum Frequency > 1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.4 ns to 12.4 ns
10 ps Increments
PECL Mode Operating Range:
V
= 3.0 V to 3.6 V with V
= 0 V
CC
EE
NECL Mode Operating Range:
V
= 0 V with V
= −3.0 V to −3.6 V
CC
EE
© Semiconductor Components Industries, LLC,2010
August, 2010 − Rev. 15
(pin 7) and V
(pin 8)
EF
CF
and V
CF
EF
pin. The 1.5 V reference voltage
as a switching reference voltage.
BB
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
V
Output Reference Voltage
BB
Pb−Free Packages are Available*
1
http://onsemi.com
MARKING
DIAGRAM*
MC100
EP196
AWLYYWWG
LQFP−32
FA SUFFIX
32
CASE 873A
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Publication Order Number:
MC100EP196/D

MC100EP196FAG Summary of contents

  • Page 1

    ... ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Publication Order Number: MC100EP196/D ...

  • Page 2

    MC100EP196 D10 ...

  • Page 3

    Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN ECL Input 5 IN ECL Input 6 V − BB ...

  • Page 4

    Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW HIGH 3. Internal pulldown resistor will provide a logic LOW if pin ...

  • Page 5

    Figure 2. Logic Diagram http://onsemi.com 5 ...

  • Page 6

    Table 5. THEORETICAL DELTA DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. Table 6. TYPICAL FTUNE DELAY PIN Input Range V ...

  • Page 7

    Figure 3. Measured Delay vs. Select Inputs Table 7. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture ...

  • Page 8

    Table 8. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

  • Page 9

    Table 9. DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

  • Page 10

    Table 10. DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

  • Page 11

    Table 11. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency max t Propagation Delay PLH D(0− PHL D(0−9) = 1023 D(0− D10 to CASCADE t Programmable ...

  • Page 12

    Using the FTUNE Analog Input The analog FTUNE pin on the EP196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital EP196. The level of resolution obtained ...

  • Page 13

    Cascading Multiple EP196s To increase the programmable range of the EP196, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP196s without the need for any external gating. Furthermore, this capability requires only one more ...

  • Page 14

    An expansion of the latch section of the block diagram is pictured in Figure 7. Use of this diagram will simplify the explanation of how the SETMIN and SETMAX circuitry works in cascade. When D10 of chip #1 in Figure ...

  • Page 15

    Table 12. CASCADED DELAY VALUE OF TWO EP196S VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...

  • Page 16

    Multi−Channel Deskewing The most practical application for EP196 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can be sent ...

  • Page 17

    ... Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP196FA MC100EP196FAG MC100EP196FAR2 MC100EP196FAR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

  • Page 18

    ... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...