W234X Cypress Semiconductor Corp, W234X Datasheet

CLOCK GEN DIR RAMBS DUAL 28TSSOP

W234X

Manufacturer Part Number
W234X
Description
CLOCK GEN DIR RAMBS DUAL 28TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Direct RAMbus Clock Generatorr
Datasheet

Specifications of W234X

Input
CMOS
Output
CMOS
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1398

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W234X
Manufacturer:
ICW
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-07232 Rev. *B
Features
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc.
Intel is a registered trademark of Intel Corporation.
• Differential clock source for Direct Rambus™ memory
• Provide synchronization flexibility: the Rambus
• Power managed output allows Rambus Channel clock
• Works with Cypress CY2210-2, CY2210-3, CY2215,
• Low-power CMOS design packaged in a 28-pin, 173-mil
Block Diagram
SYNCLKN0
PWR_DWN#
subsystem for up to 1.6-Gb/s serial data transfer rate
nel can optionally be synchronous to an external sys-
tem or processor clock
to be turned off to minimize power consumption for
mobile applications
W133, W158, W159, W161, and W167B to support Intel
architecture platforms
TSSOP package
SYNCLKN1
PCLKM0
REFCLK
MULT0:2
PCLKM1
STOP#
S0:2
Alignment
PLL
Alignment
Phase
Test
Logic
Phase
Output
Logic
Output
Logic
3901 North First Street
Dual Direct Rambus™ Clock Generator
®
Chan-
®
CLK0
CLK0#
CLK1
CLK1#
Overview
The Cypress W234 provides dual channel differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
Key Specifications
Supply Voltage: ................................... V
Operating Temperature: ................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................V
Maximum Input Frequency: ..................................... 100 MHz
Output Duty Cycle: .................................. 40/60% worst case
Output Type:........................... Rambus signaling level (RSL)
Pin Configuration
PWR_DWN#
SYNCLKN0
SYNCLKN1
VDDIPD
PCLKM0
REFCLK
PCLKM1
STOP#
San Jose
VDDIR
GND
GND
VDD
VDD
VDD
13
14
10
11
12
1
2
3
4
5
6
7
8
9
CA 95134
Revised December 21, 2002
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DD
= 3.3V ± 0.165V
408-943-2600
S0
S1
S2
GND
CLK0#
CLK0
VDD
VDD
CLK1
CLK1#
GND
MULT0
MULT1
MULT2
W234
DD
+ 0.5V

Related parts for W234X

W234X Summary of contents

Page 1

... Alignment PWR_DWN# STOP# Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07232 Rev. *B Dual Direct Rambus™ Clock Generator Overview The Cypress W234 provides dual channel differential clock signals for a Direct Rambus memory subsystem. It includes ® ...

Page 2

Pin Definitions Pin Pin Name No. Type REFCLK 2 PCLKM0 SYNCLKN0 STOP# 13 PWR_DWN# 14 MULT 0:2 17, 16, 15 CLK0, CLK0#, 23, 24, 20, CLK1, CLK1# 19 S0, S1, S2 28, 27, 26 VDDIR 1 ...

Page 3

CY2210-2 CY2210-3 CY2215 W133 W158 W159 W161 W167B RMC Pclk DDLL System Architecture and Gear Ratio Logic Figure 1 shows the Distributed Delay Lock Loop (DDLL) sys- tem architecture, including the main system clock source, the Direct Rambus clock generator ...

Page 4

CY2210-2 CY2210-3 CY2215 W133 W158 W159 W161 W167B Phase Detector Signals The DRCG Phase Detector ( ) receives two inputs from the D core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M and N dividers in the core logic are ...

Page 5

Table 3. Bypass and Test Mode Selection By Pclk Mode (int.) Normal Gnd Bypass PLLClk Test RefClk Vendor Test Vendor Test 1 0 ...

Page 6

V Turn- Test K V Turn- Clk Stop mode, the clock source is on, but the output is disabled (STOP# asserted). The VDDIPD reference input may remain on or may be grounded during the Clk Stop ...

Page 7

Timing Diagrams Power-Down Exit and Entry PWR_DWN# CLK0/CLK0# CLK1/CLK1# Output Enable Control STOP# CLK0/CLK0# CLK1/CLK1# MULT0 and/or MULT1 and/or MULT2 Document #: 38-07232 Rev POWERUP CLKON t CLKSETL clock output settled within clock enabled output ...

Page 8

Table 7. State Transition Latency Specifications Transi- tion From A Power-Down C Power-Down K Power-Down G VDD ON H VDD ON M VDD ON J Normal E Clk Stop E Clk Stop F Normal L Test N Normal B,D Normal ...

Page 9

Table 9. Supply and Reference Current Specification Parameter I “Supply” current in Power-Down state (PWR_DWN POWERDOWN I “Supply” current in Clk Stop state (STOP CLKSTOP I “Supply” current in Normal state NORMAL (STOP# = 1,PWR_DWN# = ...

Page 10

Table 12. Operating Conditions Parameter V Supply Voltage DD T Ambient Operating Temperature A t Refclk Input Cycle Time CYCLE,IN t Input Cycle-to-Cycle Jitter J,IN DC Input Duty Cycle over 10,000 Cycles IN FM Input Frequency of Modulation IN ...

Page 11

Table 13. Device Characteristics Parameter t Clock Cycle Time CYCLE t Cycle-to-Cycle Jitter at CLK/CLK# J Total Jitter over Clock Cycles 266-MHz Cycle-to-Cycle Jitter 266-MHz Total Jitter over Clock Cycles V Output ...

Page 12

... Document #: 38-07232 Rev. *B © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 13

Package Diagram 28-Pin Thin Small Shrink Outline Package (TSSOP, 173 mils) Document #: 38-07232 Rev. *B W234 Page ...

Page 14

Document Title: W234 Dual Direct Rambus™ Clock Generator Document Number: 38-07232 Issue REV. ECN NO. Date ** 110497 10/21/01 *A 111647 02/07/02 *B 122846 12/21/02 Document #: 38-07232 Rev. *B Orig. of Change Description of Change SZV Change from Spec ...

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