MC100EP195BFAR2G ON Semiconductor, MC100EP195BFAR2G Datasheet - Page 14

• Manufacturer Part Number: MC100EP195BFAR2G
• Description: IC PROGR DELAY CHIP 3.3V 32LQFP
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Programmable Delay Chipr

Specifications of MC100EP195BFAR2G

• Input: ECL, LVCMOS, LVTTL
• Output: ECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Multi−Channel Deskewing
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
Measure Unknown High Speed Device Delays
unknown delay of a device with a high degree of precision.
By combining two EP195Bs and EP31 as shown in Figure
8, the delay can be measured. The first EP195B can be set
to SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195B is triggered along with the first
EP195B and its output provides a clock signal for EP31.
The programmed delay of the second EP195B is varied to
detect the output edge from the unknown delay device.
CLOCK
CLOCK
The most practical application for EP195B is in multiple
EP195Bs provide a possible solution to measure the
Control
Logic
IN
IN
IN
IN
Control
Logic
EP195B
EP195B
Digital
Data
#1
#2
Figure 7. Multiple Channel Deskewing Diagram
Figure 8. Multiple Channel Deskewing Diagram
IN
IN
IN
IN
IN
IN
Q
Q
Q
Q
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EP195B
EP195B
EP195B
14
#N
#1
#2
Unknown Delay
be sent through each EP195B as shown in Figure 7. One signal
channel can be used as reference and the other EP195Bs can
be used to adjust the delay to eliminate the timing skews.
Nearly any high−speed system can be fine−tuned (as small as
10 ps) to reduce the skew to extremely tight tolerances.
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195B is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195B, the flip−flop will bounce between logic high and
logic low. The digital code in the second EP195B can be
directly correlated into an accurate device delay.
If the programmed delay through the second EP195B is too
Device
Q
Q
Q
Q
Q
Q
D
CLK
EP31
Q
Q