MC100EP195BFAR2G ON Semiconductor, MC100EP195BFAR2G Datasheet - Page 3

• Manufacturer Part Number: MC100EP195BFAR2G
• Description: IC PROGR DELAY CHIP 3.3V 32LQFP
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Programmable Delay Chipr

Specifications of MC100EP195BFAR2G

• Input: ECL, LVCMOS, LVTTL
• Output: ECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. PIN DESCRIPTION
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V
23, 25, 26, 27,
29, 30, 31, 32,
13, 18, 19, 22
9, 24, 28
1, 2
Pin
10
12
14
15
16
17
21
20
11
3
4
5
6
7
8
CC
and V
EE
CASCADE
CASCADE
SETMAX
SETMIN
pins must be externally connected to Power Supply to guarantee proper operation.
Name
D[0:9]
D[10]
LEN
V
V
V
V
V
EN
NC
IN
IN
Q
Q
CC
BB
EF
CF
EE
LVCMOS, LVTTL,
LVCMOS, LVTTL,
LVPECL, LVDS
LVPECL, LVDS
ECL Output
ECL Output
ECL Output
ECL Output
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
I/O
−
−
−
−
−
−
Default State
High
http://onsemi.com
Low
Low
Low
Low
Low
Low
Low
−
−
−
−
−
−
−
−
−
−
3
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to V
(Note 1)
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to V
Noninverted Differential Input. Internal 75 kW to V
Inverted Differential Input. Internal 75 kW to V
V
ECL Reference Voltage Output
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
Negative Supply Voltage. All V
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Positive Supply Voltage. All V
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Single−ended D pins LOAD / HOLD input. Internal 75 kW to V
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
V
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
V
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to V
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to V
Single−ended Output Enable Pin. Internal 75 kW to V
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
Noninverted Differential Output. Typically Terminated with 50 W to
V
Inverted Differential Output. Typically Terminated with 50 W to
V
CC
EE
EE
TT
TT
EE
. (Note 1)
. (Note 1)
.
= V
= V
. (Note 1)
CC
CC
− 2 V.
− 2 V.
TT
= V
CC
− 2 V.
TT
Description
= V
CC
EE
CC
Pins must be externally
Pins must be Externally
− 2 V.
EE
and 36.5 kW to
EE
.
EE
.
EE
EE
.
.