MC100EP195BMNR4G ON Semiconductor, MC100EP195BMNR4G Datasheet - Page 12

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MC100EP195BMNR4G

Manufacturer Part Number
MC100EP195BMNR4G
Description
IC PROGRAM DELAY 3.3V ECL 32-QFN
Manufacturer
ON Semiconductor
Series
100EPr
Type
Programmable Delay Chipr
Datasheet

Specifications of MC100EP195BMNR4G

Input
ECL, LVCMOS, LVTTL
Output
ECL
Frequency - Max
1.2GHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TFQFN Exposed Pad
Frequency-max
1.2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100EP195BMNR4GOS
MC100EP195BMNR4GOS
MC100EP195BMNR4GOSTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100EP195BMNR4G
Manufacturer:
ON Semiconductor
Quantity:
183
pictured in Figure 6. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 5 is LOW this device’s
CASCADE output will also be low while the CASCADE
output will be high. In this condition the SET MIN pin of
chip #2 will be asserted HIGH and thus all of the latches of
chip #2 will be reset and the device will be set at its minimum
delay.
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
MAX
INPUT
SET
SET
MIN
An expansion of the latch section of the block diagram is
Chip #1, on the other hand, will have both SET MIN and
D0 Q0
LEN
Set Reset
BIT 0
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
Need if Chip #3 is used
D1 Q1
LEN
Set Reset
BIT 1
D6
Figure 6. Expansion of the Latch Section of the EP195B Block Diagram
D5
EP195B
CHIP #2
D4
D2 Q2
LEN
Set Reset
BIT 2
V
EE
D3
D3 Q3
LEN
Set Reset
Figure 5. Cascading Interconnect Architecture
BIT 3
D2
TO SELECT MULTIPLEXERS
D1
V
V
V
V
NC
D0
CC
CC
CC
EE
http://onsemi.com
D4 Q4
LEN
Q
Q
Set Reset
BIT 4
12
D5 Q5
LEN
Set Reset
BIT 5
(1111111111 on the A0—A9 address bus) D10 will be
asserted to signal the need to cascade the delay to the next
EP195B device. When D10 is asserted, the SET MIN pin of
chip #2 will be deasserted and SET MAX pin asserted
resulting in the device delay to be the maximum delay.
Table 11 shows the delay time of two EP195B chips in
cascade.
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 5. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
To expand this cascading scheme to more devices, one
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
D6
D6 Q6
LEN
Set Reset
BIT 6
D5
ADDRESS BUS
D4
CHIP #1
EP195B
D7 Q7
LEN
Set Reset
BIT 7
V
EE
D3
D8 Q8
LEN
Set Reset
BIT 8
D2 D1
V
V
V
V
NC
D0
CC
CC
CC
EE
Q
Q
D9 Q9
LEN
Set Reset
BIT 9
OUTPUT

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