MC100EP195FAG ON Semiconductor, MC100EP195FAG Datasheet - Page 13

• Manufacturer Part Number: MC100EP195FAG
• Description: IC PROGRAM DELAY 3.3V ECL 32LQFP
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Programmable Delay Chipr

Specifications of MC100EP195FAG

• Input: ECL, LVCMOS, LVTTL
• Output: ECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 1.2GHz
• Function: Active Programmable Delay Line
• Supply Voltage (min): +/- 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): +/- 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC100EP195FAGOS

Cascading Multiple EP195s
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
INPUT
To increase the programmable range of the EP195,
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
Need if Chip #3 is used
D6
D5
CHIP #2
D4
EP195
V
EE
IN
IN
Q
Q
D3
Figure 5. AC Reference Measurement
Figure 6. Cascading Interconnect Architecture
t
PLH
D2
D1
V
V
V
V
NC
D0
CC
CC
CC
EE
http://onsemi.com
Q
Q
13
two EP195s. As can be seen, this scheme can easily be
expanded for larger EP195 chains. The D10 input of the
EP195 is the CASCADE control pin. With the interconnect
scheme of Figure 6 when D10 is asserted, it signals the need
for a larger programmable range than is achievable with a
single device and switches output pin CASCADE HIGH and
pin CASCADE LOW. The A11 address can be added to
generate a cascade output for the next EP195. For a 2−device
configuration, A11 is not required.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Figure 6 illustrates the interconnect scheme for cascading
D8
D9
D10
IN
IN
V
V
V
BB
EF
CF
D7
t
PHL
D6
V
V
INPP
OUTPP
D5
ADDRESS BUS
= V
= V
D4
CHIP #1
IH
EP195
(D) − V
OH
(Q) − V
V
EE
IL
(D)
D3
OL
(Q)
D2 D1
V
V
V
V
NC
D0
CC
CC
CC
EE
Q
Q
OUTPUT