MC100EP195FAG ON Semiconductor, MC100EP195FAG Datasheet - Page 3

IC PROGRAM DELAY 3.3V ECL 32LQFP

MC100EP195FAG

Manufacturer Part Number
MC100EP195FAG
Description
IC PROGRAM DELAY 3.3V ECL 32LQFP
Manufacturer
ON Semiconductor
Series
100EPr
Type
Programmable Delay Chipr
Datasheet

Specifications of MC100EP195FAG

Input
ECL, LVCMOS, LVTTL
Output
ECL
Frequency - Max
1.2GHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
1.2GHz
Function
Active Programmable Delay Line
Supply Voltage (min)
+/- 3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
+/- 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100EP195FAGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100EP195FAG
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
MC100EP195FAG
Manufacturer:
ON/安森美
Quantity:
20 000
Table 1. PIN DESCRIPTION
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V
23, 25, 26, 27,
29, 30, 31, 32,
13, 18, 19, 22
9, 24, 28
Pin
1, 2
10
12
14
15
16
17
21
20
11
3
4
5
6
7
8
CC
and V
EE
CASCADE
CASCADE
SETMAX
SETMIN
pins must be externally connected to Power Supply to guarantee proper operation.
Name
D[0:9]
D[10]
LEN
V
V
V
V
V
EN
NC
IN
IN
Q
Q
CC
BB
EF
CF
EE
LVCMOS, LVTTL,
LVCMOS, LVTTL,
ECL Output
ECL Output
ECL Output
ECL Output
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
I/O
Default State
High
Low
Low
Low
Low
Low
Low
Low
http://onsemi.com
3
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to V
(Note 1)
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to V
Noninverted Differential Input. Internal 75 kW to V
Inverted Differential Input. Internal 75 kW to V
V
ECL Reference Voltage Output
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
Negative Supply Voltage. All V
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Positive Supply Voltage. All V
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Single−ended D pins LOAD / HOLD input. Internal 75 kW to V
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
V
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
V
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to V
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to V
Single−ended Output Enable Pin. Internal 75 kW to V
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
Noninverted Differential Output. Typically Terminated with 50 W to
V
Inverted Differential Output. Typically Terminated with 50 W to
V
CC
EE
EE
TT
TT
EE
. (Note 1)
. (Note 1)
.
= V
= V
. (Note 1)
CC
CC
− 2 V.
− 2 V.
TT
= V
CC
− 2 V.
TT
Description
= V
CC
EE
CC
Pins must be externally
Pins must be Externally
− 2 V.
EE
and 36.5 kW to
EE
.
EE
.
EE
EE
.
.

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