IC PROGR DELAY CHIP 3.3V 32-QFN

MC100EP195MNG

Manufacturer Part NumberMC100EP195MNG
DescriptionIC PROGR DELAY CHIP 3.3V 32-QFN
ManufacturerON Semiconductor
Series100EP
TypeProgrammable Delay Chip
MC100EP195MNG datasheet
 


Specifications of MC100EP195MNG

InputECL, LVCMOS, LVTTLOutputECL
Frequency - Max1.2GHzVoltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case32-TFQFN Exposed PadFrequency-max1.2GHz
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
Page 1/20

Download datasheet (222Kb)Embed
Next
MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V
and V
open. For ECL operation, short V
CF
EF
V
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
EF
supply reference to V
and leave open V
CF
voltage to V
pin can be accomplished by placing a 2.2 kW resistor
CF
between V
and V
for a 3.3 V power supply.
CF
EE
The V
pin, an internally generated voltage supply, is available to
BB
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
and V
via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V
should be left open.
BB
The 100 Series contains temperature compensation.
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range:
V
= 3.0 V to 3.6 V with V
CC
NECL Mode Operating Range:
V
= 0 V with V
= −3.0 V to −3.6 V
CC
EE
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 18
(pin 7) and V
(pin 8)
EF
CF
and
CF
pin. The 1.5 V reference
EF
as a switching reference voltage.
BB
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
= 0 V
EE
V
Output Reference Voltage
BB
Pb−Free Packages are Available
1
http://onsemi.com
MARKING
DIAGRAM*
MCXXX
EP195
AWLYYWWG
LQFP−32
FA SUFFIX
32
CASE 873A
1
1
MCXXX
1
32
EP195
AWLYYWWG
QFN32
G
MN SUFFIX
CASE 488AM
XXX
= 10 or 100
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Publication Order Number:
MC10EP195/D

MC100EP195MNG Summary of contents

  • Page 1

    MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable ...

  • Page 2

    D10 3 MC10EP195 IN 4 MC100EP195 Figure 1. 32−Lead LQFP Pinout (Top View) 32 ...

  • Page 3

    Table 1. PIN DESCRIPTION Pin Name I/O 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, 29, 30, 31, 32, ECL Input D[10] LVCMOS, LVTTL, ECL Input 4 IN ECL Input 5 IN ECL Input 6 V − BB ...

  • Page 4

    Table 2. CONTROL PIN Pin State EN LOW (Note 3) HIGH LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH 3. Internal pulldown resistor will provide a logic LOW ...

  • Page 5

    Figure 3. Logic Diagram http://onsemi.com 5 ...

  • Page 6

    Table 6. THEORETICAL DELAY VALUES D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. SETMIN SETMAX ...

  • Page 7

    −3.3 V 8000.0 EE 7000.0 6000.0 5000.0 4000.0 3000.0 2000.0 1000.0 0.0 0.0 100.0 Table 7. MAXIMUM RATINGS Symbol Parameter V Positive Mode Power Supply CC V ...

  • Page 8

    Table 8. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 9

    Table 9. 10EP DC CHARACTERISTICS, NECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note 11 Output LOW Voltage (Note 11 Input HIGH Voltage (Single−Ended) IH LVNECL V Input LOW Voltage (Single−Ended) ...

  • Page 10

    Table 10. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Negative Power Supply Current EE V Output HIGH Voltage (Note 14 Output LOW Voltage (Note 14 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 11

    Table 11. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Negative Power Supply Current EE (Note 17) V Output HIGH Voltage (Note 18 Output LOW Voltage (Note 18 Input HIGH Voltage (Single−Ended Input LOW Voltage ...

  • Page 12

    Table 12. AC CHARACTERISTICS Symbol Characteristic f Maximum Frequency max t Propagation Delay PLH D(0−10 PHL D(0−10) = 1023 D(0−10 CASCADE t Programmable Range ...

  • Page 13

    Cascading Multiple EP195s To increase the programmable range of the EP195, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195s without the need for any external gating. Furthermore, this capability requires only one more ...

  • Page 14

    An expansion of the latch section of the block diagram is pictured in Figure 7. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 6 is LOW this ...

  • Page 15

    Table 13. Delay Value of Two EP195 Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 ...

  • Page 16

    Multi−Channel Deskewing The most practical application for EP195 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can Digital Data ...

  • Page 17

    ... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10EP195FA MC10EP195FAG MC10EP195FAR2 MC10EP195FAR2G MC10EP195MNG MC10EP195MNR4G MC100EP195FA MC100EP195FAG MC100EP195FAR2 MC100EP195FAR2G MC100EP195MNG MC100EP195MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

  • Page 18

    Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

  • Page 19

    −T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...

  • Page 20

    ... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...