W40S11-02H Cypress Semiconductor Corp, W40S11-02H Datasheet
W40S11-02H
Specifications of W40S11-02H
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W40S11-02H Summary of contents
Page 1
... DC to 133-MHz operation • Single 3.3V supply voltage • Low power CMOS design packaged in a 28-pin, 209-mil SSOP (Shrink Small Outline Package) Overview The Cypress W40S11- low-voltage, ten-output clock buffer. Output buffer impedance is approximately 15 , which is ideal for driving SDRAM DIMMs. Block Diagram SDATA ...
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... C section of this data sheet. Internal 250-k pull-up resistor. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. Output Enable: Internal 250-k pull-up resistor. Three-states outputs when LOW. 2 W40S11- section ...
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... Data is written to the W40S11-02 in ten bytes of eight bits each. Bytes are written in the order shown in Table 1. Byte Description Commands the W40S11-02 to accept the bits in Data Bytes 0–6 for in- ternal register configuration. Since other devices may exist on the same common serial data bus necessary to have a specific slave address for each potential receiver ...
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... Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) 4 W40S11-02 Bit Control Low Active Low Active Low Active Low ...
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... Electrical Requirements Figure 1 illustrates electrical characteristics for the serial inter- face bus used with the W40S11-02. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resis- ...
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... A write sequence is initiated by a “start bit” as shown in Figure 3. A “stop bit” signifies that a transmission has ended. As stated previously, the W40S11-02 sends an “acknowledge” pulse after receiving eight data bits in each byte as shown in Figure 4. SDATA ...
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Signaling from System Core Logic Start Condition Slave Address (First Byte) LSB MSB SDATA SCLOCK SDATA Signaling by Clock Device SDATA t t LOW DSU t ...
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... Description T = 0°C to +70° 3.3V± Test Condition/Comments at 66 MHz at 100 MHz [ – 1. 1.5V OH internal pull-up resistor (V – 0.8V W40S11-02 Rating Unit –0.5 to +7.0 V –65 to +150 ° +70 °C –55 to +125 °C Min Typ Max Unit 120 160 mA 185 220 –0.3 ...
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... Capacitance Test Load = 30 pF Test Condition Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured at 1.5V Package Name Package Type H 28-pin SSOP (209-mil) X 28-pin TSSOP (173-mil) 9 W40S11-02 Min Typ Max Unit 0 133 MHz 1.5 4.0 V/ns 1.5 4.0 V/ns 250 ...
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... Package Diagrams 28-Pin Shrink Small Outline Package (TSSOP, 173-mil) 10 W40S11-02 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W40S11-02 ...