AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet
AD9511BCPZ
Specifications of AD9511BCPZ
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AD9511BCPZ Summary of contents
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FEATURES Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCP ) extends tuning range S Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 ...
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AD9511 TABLE OF CONTENTS Specifications..................................................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Phase Noise .......................................................... 9 Clock Output Additive Time Jitter........................................... 12 PLL and Distribution Phase Noise and ...
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Single-Chip Synchronization.....................................................40 SYNCB—Hardware SYNC ....................................................40 Soft SYNC—Register 58h<2> ...............................................40 Multichip Synchronization ........................................................40 Serial Control Port ..........................................................................41 Serial Control Port Pin Descriptions........................................41 General Operation of Serial Control Port ...............................41 Framing a Communication Cycle with CSB .......................41 Communication Cycle—Instruction Plus Data..................41 Write ...
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AD9511 SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 Minimum (min) and maximum (max) values are given over full V PLL CHARACTERISTICS Table 1. Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, ...
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Parameter NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL kHz PFD Frequency @ 2 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency ...
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AD9511 CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2; Differential Output Frequency Output High Voltage ( Output Low Voltage ( Output Differential Voltage ( LVDS CLOCK OUTPUTS OUT3, OUT4; Differential Output ...
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TIMING CHARACTERISTICS Table 4. Parameter LVPECL Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUT PECL Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS 2 OUT1 ...
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AD9511 Parameter DELAY ADJUST 4 Shortest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL 4 Longest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature 5 Long Delay Range Zero Scale ...
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CLOCK OUTPUT PHASE NOISE Table 5. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ ...
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AD9511 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz ...
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Parameter @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset ...
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AD9511 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = ...
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Parameter CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = ...
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AD9511 Parameter CLK1 = 400 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4 MHz (B Output On) 1 DELAY BLOCK ADDITIVE TIME JITTER 100 MHz Output ...
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SERIAL CONTROL PORT Table 8. Parameter CSB, SCLK (INPUTS) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic ...
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AD9511 STATUS PIN Table 10. Parameter Min OUTPUT CHARACTERISTICS Output Voltage High (V ) 2.7 OH Output Voltage Low ( MAXIMUM TOGGLE RATE ANALOG LOCK DETECT Capacitance POWER Table 11. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION POWER DISSIPATION ...
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TIMING DIAGRAMS t CLK1 CLK1 t PECL t LVDS t CMOS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev. ...
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AD9511 ABSOLUTE MAXIMUM RATINGS Table 12. With Respect to Parameter or Pin VS GND VCP GND VCP V S REFIN, REFINB GND RSET GND CPRSET GND CLK1, CLK1B, CLK2, CLK2B GND CLK1 CLK1B CLK2 CLK2B SCLK, SDIO, SDO, CSB GND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FUNCTION Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. REFIN 1 ...
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AD9511 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 REFIN PLL Reference Input. 2 REFINB Complementary PLL Reference Input 18, 22, VS Power Supply (3.3 V). 23, 25, 28, 29, 32, 33, 36, 39, 40, ...
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TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain ...
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AD9511 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 DEFAULT – 3 LVPECL + 2 LVDS (DIV ON) 0.5 3 LVPECL + 2 LVDS (DIV BYPASSED) 0.4 3 LVPECL (DIV ON) 2 LVDS (DIV ON) 0.3 0 400 OUTPUT FREQUENCY (MHz) Figure 7. Power ...
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CENTER 245.75MHz 30kHz/ Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, FOUT = 245.76 MHz, FPFD = 1.2288 MHz 25 200 0 ...
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AD9511 VERT 500mV/DIV Figure 18. LVPECL Differential Output @ 800 MHz VERT 100mV/DIV Figure 19. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 20. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.7 1.6 1.5 1.4 ...
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OFFSET (Hz) Figure 24. Additive Phase Noise—LVPECL DIV1, 245.76 MHz Distribution Section Only –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k ...
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AD9511 TYPICAL MODES OF OPERATION PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION This is the most common operational mode for the AD9511. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. ...
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PLL WITH EXTERNAL VCO AND BAND-PASS FILTER FOLLOWED BY CLOCK DISTRIBUTION An external band-pass filter may be used to try to improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate to optimize cost ...
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AD9511 REFIN 250MHz REFINB FUNCTION CLK1 1.6GHz CLK1B SCLK SDIO SDO CSB VS GND RSET DISTRIBUTION AD9511 REF R DIVIDER PHASE FREQUENCY DETECTOR N DIVIDER SYNCB, RESETB PDB PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 /1, /2, ...
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FUNCTIONAL DESCRIPTION OVERALL Figure 33 shows a block diagram of the AD9511. The chip combines a programmable PLL core with a configurable clock distribution system. A complete PLL requires the addition of a suitable external VCO (or VCXO) and loop ...
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AD9511 Table 14. PLL Prescaler Modes Mode (FD = Fixed Divide DM = Dual Modulus) Value in 0Ah<4:2> FD 000 FD 001 010 011 100 ...
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Phase Frequency Detector (PFD) and Charge Pump The PFD takes inputs from the R counter and the N counter ( and produces an output proportional to the phase and frequency difference between them. Figure 36 is ...
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AD9511 PLL Analog Lock Detect An analog lock detect (ALD) signal may be selected. When ALD is selected, the signal at the STATUS pin is either an open- drain P-channel (08h<5:2> = 1100b open-drain N- channel (08h<5:2> = ...
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When the SYNCB function is selected, the FUNCTION pin does not act as either RESETB or PDB. PDB: 58h<6:5> = 11b The FUNCTION pin may also be programmed to work as an asynchronous full power-down, PDB. Even in ...
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AD9511 Table 17. Duty Cycle and Divide Ratio LO<7:4> Divide Ratio Duty Cycle (%) ...
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LO<7:4> Divide Ratio Duty Cycle (%) ...
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AD9511 LO<7:4> Divide Ratio Duty Cycle (%) ...
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Divider Phase Offset The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers, which set the phase and start high/low bit for each output. These ...
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AD9511 DIV = 18 Unique Phase Offsets Are Phase = 10, 11, 12, 13, 14, 15, 16, 17 Phase offsets may be related to degrees by calculating the phase step ...
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Figure 42. LVDS Output Simplified Equivalent Circuit POWER-DOWN MODES Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9511. When the PDB mode is enabled, a chip power-down ...
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AD9511 RESET MODES The AD9511 has several ways to force the chip into a reset condition. Power-On Reset—Start-Up Conditions when VS is Applied A power-on reset (POR) is issued when the VS power supply is turned on. This initializes the ...
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SERIAL CONTROL PORT The AD9511 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9511 serial control port is compatible with most synchronous transfer formats, including both ...
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AD9511 writing to Register 5Ah<0> = 1b. This update bit is self-clearing (it is not required to write clear it). Since any number of bytes of data can be changed before issuing an update command, the ...
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Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 A12 = 0 A11 = 0 CSB SCLK DON'T CARE SDIO R A12 A11 A10 ...
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AD9511 t S CSB t DS SCLK SDIO BI N Table 22. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH ...
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REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 23. AD9511 Register Map Addr (Hex) Parameter Bit 7 (MSB) 00 Serial SDO Inactive Control Port (Bidirectional Configuration Mode) 01, 02, 03 PLL 04 A Counter Not Used 05 B Counter Not Used ...
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AD9511 Addr (Hex) Parameter Bit 7 (MSB) OUTPUTS 3D LVPECL OUT0 3E LVPECL OUT1 3F LVPECL OUT2 40 LVDS_CMOS Not Used OUT 3 41 LVDS_CMOS Not Used OUT 4 42, 43, 44 CLK1 AND CLK2 45 Clocks Select, Not Used ...
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REGISTER MAP DESCRIPTION Table 24 lists the AD9511 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the ...
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AD9511 Reg. Addr. (Hex) Bit(s) Name 08 <5:2> PLL Mux Control 08 <6> Phase-Frequency Detector (PFD) Polarity 08 <7> 09 <0> Reset All Counters 0 = Normal (Default Reset R, A, and B Counters. 09 <1> N-Counter Reset ...
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Reg. Addr. (Hex) Bit(s) Name Description 0A <1:0> PLL Power-Down 01 = Asynchronous Power-Down (Default). <1> <4:2> Prescaler Value (P/P+1) <4> Dual Modulus ...
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AD9511 Reg. Addr. (Hex) Bit(s) Name Fine Delay Adjust 34 <0> Delay Control OUT4 34 <7:1> 35 <2:0> Ramp Current OUT4 35 <5:3> Ramp Capacitor OUT4 35 <7:6> 36 <0> 36 <5:1> Delay Fine Adjust OUT4 36 <7:6> <7:0> 37 ...
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Reg. Addr. (Hex) Bit(s) Name Description 3D (3E) (3F) <3:2> Output Level Output Single-Ended Voltage Levels for LVPECL Outputs. LVPECL OUT0 (OUT1) (OUT2) <3> (3E) (3F) <7:4> Not Used 40 (41) <0> Power-Down Power-Down Bit ...
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AD9511 Reg. Addr. (Hex) Bit(s) Name <3:0> Divider High 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <7:4> Divider Low 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <3:0> Phase Offset 4B OUT0 (4D) (OUT1) (4F) ...
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Reg. Addr. (Hex) Bit(s) Name Description 58 <2> Soft SYNC Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s polarity is reversed. That is, a high level forces selected outputs into ...
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AD9511 POWER SUPPLY The AD9511 requires a 3.3 V ± 5% power supply for V The tables in the Specifications section give the performance expected from the AD9511 with the power supply voltage within this range. The absolute maximum range ...
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APPLICATIONS USING THE AD9511 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer; any ...
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AD9511 Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9511 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent ...
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... PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9511BCPZ −40°C to +85°C 1 AD9511BCPZ-REEL7 −40°C to +85°C AD9511/PCB AD9511-VCO/PCB Pb-free part. 0.60 MAX 37 36 6.75 BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP ...
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AD9511 NOTES Rev Page ...
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NOTES Rev Page AD9511 ...
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AD9511 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05286–0–6/05(A) Rev Page ...