AD9514BCPZ Analog Devices Inc, AD9514BCPZ Datasheet

IC CLOCK DIST 3OUT PLL 32LFCSP

AD9514BCPZ

Manufacturer Part Number
AD9514BCPZ
Description
IC CLOCK DIST 3OUT PLL 32LFCSP
Manufacturer
Analog Devices Inc
Type
Fanout Buffer (Distribution), Dividerr
Datasheet

Specifications of AD9514BCPZ

Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
Yes/Yes
Input
Differential
Output
CMOS, LVDS, LVPECL
Frequency - Max
1.6GHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Frequency-max
1.6GHz
No. Of Multipliers / Dividers
3
No. Of Amplifiers
4
Supply Voltage Range
3.135V To 3.465V
Slew Rate
1V/ns
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9514/PCBZ - BOARD EVAL CLOCK 3CH AD9514
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9514BCPZ
Manufacturer:
ADI
Quantity:
526
Part Number:
AD9514BCPZ-REEL7
Manufacturer:
AD
Quantity:
3 391
FEATURES
1.6 GHz differential clock input
3 programmable dividers
2 independent 1.6 GHz LVPECL clock outputs
1 independent 800 MHz/250 MHz LVDS/CMOS clock output
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9514 features a multi-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with demanding
phase noise and jitter requirements also benefit from this part.
There are three independent clock outputs. Two of the outputs
are LVPECL, and the third output can be set to either LVDS or
CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the
third output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to another clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Divide-by in range from1 to 32
Phase select for coarse delay adjust
Additive broadband output jitter 225 fs rms
Additive broadband output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Dividers, Delay Adjust, Three Outputs
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SYNCB
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9514 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ V
⅔ V
The AD9514 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
1.6 GHz Clock Distribution IC,
CLKB
CLK
S
. V
VREF
S
(3.3 V) and GND (0 V) provide the other two logic levels.
FUNCTIONAL BLOCK DIAGRAM
RSET
S10 S9
VS
S8
© 2005 Analog Devices, Inc. All rights reserved.
/1. . . /32
/1. . . /32
/1. . . /32
S7
S
. The VREF pin provides a level of
Figure 1.
GND
SETUP LOGIC
S6
S5
AD9514
S4
Δ
t
S3
S2
AD9514
LVPECL
LVPECL
LVDS/CMOS
www.analog.com
S1
S0
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B

Related parts for AD9514BCPZ

AD9514BCPZ Summary of contents

Page 1

FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust 2 independent 1.6 GHz LVPECL clock outputs Additive broadband output jitter 225 fs rms 1 independent 800 MHz/250 MHz ...

Page 2

AD9514 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Clock Input.................................................................................... 3 Clock Outputs ............................................................................... 3 Timing Characteristics ................................................................ 4 Clock Output Phase Noise .......................................................... ...

Page 3

SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 and maximum (max) values are given over full V CLOCK INPUT Table 1. Parameter CLOCK INPUT (CLK) Input Frequency 1 1 Input Sensitivity Input Common-Mode Voltage, ...

Page 4

AD9514 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter LVPECL Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUT PECL Divide = 1 Divide = 2 − ...

Page 5

Parameter Zero Scale Delay Time Zero Scale Variation with Temperature 3 Full Scale Time Delay Full Scale Variation with Temperature Linearity, DNL Linearity, INL 1 This is the difference between any two similar delay paths within ...

Page 6

AD9514 Parameter CLK = 491.52 MHz, OUT = 245.76 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK = 245.76 MHz, ...

Page 7

Parameter CLK = 491.52 MHz, OUT = 122.88 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK ...

Page 8

AD9514 Parameter CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset ...

Page 9

Parameter CLK = 400 MHz LVDS (OUT2) = 100 MHz Divide = 4 Both LVPECL = 50 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK = 400 MHz CMOS (OUT2) = 100 MHz Divide = 4 CLK = 400 MHz CMOS ...

Page 10

AD9514 SYNCB, VREF, AND SETUP PINS Table 6. Parameter Min SYNCB Logic High 2.7 Logic Low Capacitance VREF Output Voltage 0. S10 Levels 0 1/3 0 2 ...

Page 11

TIMING DIAGRAMS t CLK CLK t PECL t LVDS t CMOS Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev. ...

Page 12

AD9514 ABSOLUTE MAXIMUM RATINGS Table 8. With Respect to Parameter or Pin VS GND RSET GND CLK GND CLK CLKB OUT0, OUT1, OUT2 GND FUNCTION GND STATUS GND 1 Junction Temperature Storage Temperature Lead Temperature (10 sec) ESD CAUTION ESD ...

Page 13

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS 1 CLK 2 CLKB 3 AD9514 VS 4 TOP VIEW (Not to Scale) SYNCB 5 VREF 6 S10 Figure 6. 32-Lead LFCSP Pin Configuration Note that the exposed paddle on this ...

Page 14

AD9514 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain ...

Page 15

TYPICAL PERFORMANCE CHARACTERISTICS 0.4 2 LVPECL (DIV ON) 0.3 2 LVPECL (DIV = 1) 0.2 1 LVDS (DIV ON) 0.1 400 800 OUTPUT FREQUENCY (MHz) Figure 8. Power vs. Frequency—LVPECL, LVDS START 300kHz STOP 5GHz Figure 9. CLK Smith Chart ...

Page 16

AD9514 VERT 500mV/DIV Figure 11. LVPECL Differential Output @ 1600 MHz VERT 100mV/DIV Figure 12. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.7 1.6 1.5 1.4 ...

Page 17

OFFSET (Hz) Figure 17. Additive Phase Noise—LVPECL Divide = 1, 245.76 MHz –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k OFFSET ...

Page 18

AD9514 FUNCTIONAL DESCRIPTION OVERALL The AD9514 provides for the distribution of its input clock three outputs simultaneously. OUT0 and OUT1 are LVPECL levels. OUT2 can be set to either LVDS or CMOS levels. Each output has its ...

Page 19

Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles. The ...

Page 20

AD9514 Table 10. S0—OUT2 Delay S0 Delay Full Scale 0 Off (Bypassed) 1/3 1 Table 11. S1, S2—Output Select OUT0 OUT1 S1 S2 LVPECL LVPECL 0 0 OFF 410 mV 1/3 0 790 ...

Page 21

Table 13. S5, S6—OUT2 Divide or OUT1 Phase S2 ≠ 0 OUT2 Divide (Duty Cycle ) 1 (50%) 2 (33 (50%) 0 1/3 5 (40%) 1/3 1/3 ...

Page 22

AD9514 DIVIDER PHASE OFFSET The phase of OUT1 or OUT2 can be selected, depending on the divide ratio and output configuration chosen. This allows, for example, the relative phase of OUT0 and OUT1 to be set. After a SYNC operation ...

Page 23

When the delay block is OFF (bypassed also powered down. OUTPUTS The AD9514 offers three different output level choices: LVPECL, LVDS, and CMOS. OUT0/OUT0B and OUT1/ OUT1B are LVPECL differential outputs. There are three amounts of LVPECL differential ...

Page 24

AD9514 Exposed Metal Paddle The exposed metal paddle on the AD9514 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The exposed paddle ...

Page 25

APPLICATIONS USING THE AD9514 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer, and ...

Page 26

AD9514 LVDS CLOCK DISTRIBUTION The AD9514 provides one clock output (OUT2) that is selectable as either CMOS or LVDS levels. Low voltage differential signaling ( LVDS differential output option for OUT2. LVDS uses a current mode output stage. ...

Page 27

PHASE NOISE AND JITTER MEASUREMENT SETUPS WENZEL EVALUATION BOARD OSCILLATOR SPLITTER 0° ZESC-2-11 EVALUATION BOARD WENZEL OSCILLATOR ⎡ V ⎢ A_RMS ⎢ ⎣ J_RMS where the rms time jitter. j_RMS SNR is the signal-to-noise ratio. ...

Page 28

... SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9514BCPZ −40°C to +85°C 1 AD9514BCPZ-REEL7 −40°C to +85°C AD9514/PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 0.60 MAX ...

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