AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet
AD9510BCPZ
Specifications of AD9510BCPZ
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AD9510BCPZ Summary of contents
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FEATURES Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCP ) extends tuning range S Two 1.6 GHz, differential clock inputs 8 programmable dividers, 1 ...
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AD9510 TABLE OF CONTENTS Specifications..................................................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Phase Noise .......................................................... 9 Clock Output Additive Time Jitter........................................... 12 PLL and Distribution Phase Noise and ...
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Single-Chip Synchronization.....................................................41 SYNCB—Hardware SYNC ....................................................41 Soft SYNC—Register 58h<2> ...............................................41 Multichip Synchronization ........................................................41 Serial Control Port ..........................................................................42 Serial Control Port Pin Descriptions........................................42 General Operation of Serial Control Port ...............................42 Framing a Communication Cycle with CSB .......................42 Communication Cycle—Instruction Plus Data..................42 Write ...
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AD9510 SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 Minimum (min) and maximum (max) values are given over full V PLL CHARACTERISTICS Table 1. Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, ...
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Parameter NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL kHz PFD Frequency @ 2 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency ...
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AD9510 CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3; Differential Output Frequency Output High Voltage ( Output Low Voltage ( Output Differential Voltage ( LVDS CLOCK OUTPUTS OUT4, OUT5, OUT6, ...
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TIMING CHARACTERISTICS Table 4. Parameter LVPECL Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUT PECL Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS 2 OUT1 ...
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AD9510 Parameter 4 DELAY ADJUST 5 Shortest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL 5 Longest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature 6 Long Delay Range Zero ...
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CLOCK OUTPUT PHASE NOISE Table 5. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ ...
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AD9510 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz ...
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Parameter @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset ...
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AD9510 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = ...
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Parameter CLK1 = 400 MHz LVDS (OUT4, OUT7) = 100 MHz Divide Ratio = 4 All Other LVDS = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT5, OUT6) = 100 MHz Divide Ratio = 4 ...
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AD9510 Parameter CLK1 = 400 MHz Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz All Other CMOS = 50 MHz (B Output On) 1 DELAY BLOCK ADDITIVE TIME ...
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SERIAL CONTROL PORT Table 8. Parameter CSB, SCLK (INPUTS) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic ...
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AD9510 STATUS PIN Table 10. Parameter Min OUTPUT CHARACTERISTICS Output Voltage High (V ) 2.7 OH Output Voltage Low ( MAXIMUM TOGGLE RATE ANALOG LOCK DETECT Capacitance POWER Table 11. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION Power Dissipation ...
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TIMING DIAGRAMS t CLK1 CLK1 t PECL t LVDS t CMOS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev. ...
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AD9510 ABSOLUTE MAXIMUM RATINGS Table 12. With Respect to Parameter or Pin VS GND VCP GND VCP V S REFIN, REFINB GND RSET GND CPRSET GND CLK1, CLK1B, CLK2, CLK2B GND CLK1 CLK1B CLK2 CLK2B SCLK, SDIO, SDO, CSB GND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FUNCTION Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. REFIN 1 ...
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AD9510 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 REFIN PLL Reference Input. 2 REFINB Complementary PLL Reference Input 12, 22, GND Ground. 27, 32, 49, 50, 55 13, 23, 26, VS ...
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TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount ...
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AD9510 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 4 LVPECL + 4 LVDS (DIV ON) 0.7 4 LVPECL + 4 LVDS (DIV BYPASSED) 0.6 0.5 DEFAULT–3 LVPECL + 2 LVDS (DIV ON) 0.4 4 LVDS ONLY (DIV ON) 0.3 4 LVPECL ONLY (DIV ...
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CENTER 245.75MHz 30kHz/ Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, FOUT = 245.76 MHz, FPFD = 1.2288 MHz 25 200 0 ...
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AD9510 VERT 500mV/DIV Figure 18. LVPECL Differential Output @ 800 MHz VERT 100mV/DIV Figure 19. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 20. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.4 1.4 1.4 1.4 ...
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OFFSET (Hz) Figure 24. Additive Phase Noise—LVPECL DIV 1, 245.76 MHz; Distribution Section Only –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k ...
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AD9510 TYPICAL MODES OF OPERATION PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION This is the most common operational mode for the AD9510. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. ...
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PLL WITH EXTERNAL VCO AND BAND-PASS FILTER FOLLOWED BY CLOCK DISTRIBUTION An external band-pass filter may be used to try to improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate to optimize cost ...
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AD9510 REFIN 250MHz REFINB FUNCTION CLK1 1.6GHz CLK1B SCLK SDIO SDO CSB VS GND RSET DISTRIBUTION AD9510 REF R DIVIDER PHASE FREQUENCY DETECTOR N DIVIDER SYNCB, RESETB, PDB PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 /1, /2, ...
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FUNCTIONAL DESCRIPTION OVERALL Figure 33 shows a block diagram of the AD9510. The chip combines a programmable PLL core with a configurable clock distribution system. A complete PLL requires the addition of a suitable external VCO (or VCXO) and loop ...
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AD9510 Table 14. PLL Prescaler Modes Mode (FD = Fixed Divide DM = Dual Modulus) Value in 0Ah<4:2> FD 000 FD 001 010 011 100 ...
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Table 16 R—Smallest Values for REF ...
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AD9510 ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN) ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN) LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH) LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW) PLL Analog Lock Detect An analog lock detect (ALD) signal may ...
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FUNCTION PIN The FUNCTION pin (16) has three functions that are selected by the value in Register 58h<6:5>. This pin is internally pulled down kΩ resistor. If this pin is left NC, the part is in reset ...
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AD9510 Setting the Divide Ratio The divide ratio is determined by the values written via the SCP to the registers that control each individual output, OUT0 to OUT7. These are the even numbered registers beginning at 48h and going through ...
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LO <7:4> Divide Ratio Duty Cycle (%) ...
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AD9510 LO <7:4> Divide Ratio Duty Cycle (%) ...
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LO <7:4> Divide Ratio Duty Cycle (%) 48h to 56h HI<3:0> Divide Ratio ...
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AD9510 Divider Phase Offset The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers which set the phase and start high/low bit for each output. ...
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Unique Phase Offsets Are Phase = DIV = 18 Unique Phase Offsets Are Phase = 10, 11, 12, 13, 14, 15, 16, 17 ...
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AD9510 3.5mA OUT OUTB 3.5mA Figure 42. LVDS Output Simplified Equivalent Circuit POWER-DOWN MODES Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9510. When the PDB mode is enabled, ...
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RESET MODES The AD9510 has several ways to force the chip into a reset condition. Power-On Reset—Start-Up Conditions when V Applied A power-on reset (POR) is issued when the V turned on. This initializes the chip to the power-on conditions ...
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AD9510 SERIAL CONTROL PORT The AD9510 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9510 serial control port is compatible with most synchronous transfer formats, including ...
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Phase offsets or divider synchronization will not become effective until a SYNC is issued (see the Single-Chip Synchronization section). Read If the instruction word is for a ...
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AD9510 Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 A12 = 0 A11 = 0 CSB SCLK DON'T CARE SDIO R A12 A11 A10 A9 A8 ...
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S CSB t DS SCLK SDIO Table 22. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of ...
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AD9510 REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 23. AD9510 Register Map Addr (Hex) Parameter Bit 7 (MSB) 00 Serial SDO Inactive Control Port (Bidirectional Configuration Mode PLL 04 A Counter Not Used 05 B Counter Not ...
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Addr (Hex) Parameter Bit 7 (MSB) 3A Delay Fine Not Used Adjust 6 3B OUTPUTS 3C LVPECL OUT0 3D LVPECL OUT1 3E LVPECL OUT2 3F LVPECL OUT3 40 LVDS_CMOS Not Used OUT 4 41 LVDS_CMOS Not Used OUT 5 42 ...
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AD9510 Addr (Hex) Parameter Bit 7 (MSB) 55 Divider 6 Bypass 56 Divider 7 57 Divider 7 Bypass FUNCTION 58 FUNCTION Not Used Pin and Sync 59 5A Update Registers END Bit 6 Bit 5 Bit 4 Bit 3 No ...
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REGISTER MAP DESCRIPTION Table 24 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the ...
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AD9510 Reg. Addr. (Hex) Bit(s) Name Description 08 <5:2> PLL Mux Control <5> MUXOUT is the PLL portion of the STATUS output MUX 08 ...
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Reg. Addr. (Hex) Bit(s) Name Description 0A <4:2> Prescaler Value (P/P+1) <4> Dual Modulus Fixed Divide. 0A <5> Not Used 0A <6> B Counter Bypass Only valid when ...
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AD9510 Reg. Addr. (Hex) Bit(s) Name Description (39) (OUT6) <2> <5:3> Ramp Capacitor Selects the Number of Capacitors in Ramp Generation Circuit 35 OUT5 More Capacitors => Slower Ramp (39) (OUT6) <5> ...
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Reg. Addr. (Hex) Bit(s) Name Description (3F) (OUT2) (OUT3) <3> <7:4> Not Used (3D) (3E) (3F) 40 <0> Power-Down Power-Down Bit for Both Output and LVDS Driver 0 = LVDS/CMOS on (Default LVDS/CMOS ...
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AD9510 Reg. Addr. (Hex) Bit(s) Name Description 45 <0> Clock Select 0: CLK2 Drives Distribution Section 1: CLK1 Drives Distribution Section (Default) 45 <1> CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b) 45 <2> CLK2 Power-Down ...
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Reg. Addr. (Hex) Bit(s) Name Description <5> Force Forces Individual Outputs to the State Specified in Start (Above) This Function Requires That Nosync (Below) Also Be Set (Default = 0b) 49 OUT0 (4B) (OUT1) (4D) (OUT2) (4F) (OUT3) (51) (OUT4) ...
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AD9510 POWER SUPPLY The AD9510 requires a 3.3 V ± 5% power supply for V The tables in the Specifications section give the performance expected from the AD9510 with the power supply voltage within this range. The absolute maximum range ...
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APPLICATIONS USING THE AD9510 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer; any ...
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AD9510 Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9510 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent ...
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... PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9510BCPZ −40°C to +85°C 1 AD9510BCPZ-REEL7 −40°C to +85°C AD9510/PCB AD9510-VCO/PCB Pb-free part. 0.60 MAX 49 48 8.75 BSC SQ 0.45 0. 0.35 0.80 MAX 0.65 TYP ...
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AD9510 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05046–0–5/05(A) Rev Page ...