MC100EL15DG ON Semiconductor, MC100EL15DG Datasheet

IC CLOCK DISTRIB CHIP 1:4 16SOIC

MC100EL15DG

Manufacturer Part Number
MC100EL15DG
Description
IC CLOCK DISTRIB CHIP 1:4 16SOIC
Manufacturer
ON Semiconductor
Series
100ELr
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of MC100EL15DG

Number Of Circuits
1
Ratio - Input:output
2:4
Differential - Input:output
Yes/Yes
Input
ECL, PECL
Output
ECL, PECL
Frequency - Max
1.25GHz
Voltage - Supply
4.2 V ~ 5.7 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
1.25GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC100EL15DGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100EL15DG
Manufacturer:
ON Semiconductor
Quantity:
110
MC10EL15, MC100EL15
5V ECL 1:4 Clock
Distribution Chip
designed explicitly for low skew clock distribution applications. The
V
only. For single-ended input conditions, the unused differential input is
connected to V
AC coupled inputs. When used, decouple V
capacitor and limit current sourcing or sinking to 0.5 mA. When not used,
V
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open and pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock
input.
only be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 5
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
BB
BB
The MC10EL/100EL15 is a low skew 1:4 clock distribution chip
The EL15 features a multiplexed clock input to allow for the
The common enable (EN) is synchronous so that the outputs will
The 100 series contains temperature compensation.
with V
with V
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN.
Pb−Free Packages are Available*
pin, an internally generated voltage supply, is available to this device
should be left open.
EE
EE
= −4.2 V to −5.7 V
= 0 V
BB
as a switching reference voltage. V
CC
CC
= 4.2 V to 5.7 V
= 0 V
BB
and V
BB
CC
may also rebias
via a 0.01 mF
1
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Application Note AND8002/D.
AWLYWW
10EL15G
ORDERING INFORMATION
A
WL
YY
WW
G
MARKING DIAGRAMS*
http://onsemi.com
16
CASE 751B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
D SUFFIX
SO−16
1
Publication Order Number:
100EL15G
AWLYWW
MC10EL15/D

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MC100EL15DG Summary of contents

Page 1

... Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN. • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 5 ...

Page 2

V EN SCLK CLK Figure 1. Logic Diagram and Pinout Assignment Table 1. PIN DESCRIPTION PIN FUNCTION CLK, CLK ECL Diff Clock Inputs SCLK ECL Scan Clock Input EN ECL Sync ...

Page 3

Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 4

Table 6. 10EL SERIES NECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

Page 5

Table 8. 100EL SERIES NECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 13 Output LOW Voltage (Note 13 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

Page 6

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10EL15D MC10EL15DG MC10EL15DR2 MC10EL15DR2G MC100EL15D MC100EL15DG MC100EL15DR2 MC100EL15DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

Page 7

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 8

... American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ...

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