MC100EL14DWR2G

Manufacturer Part NumberMC100EL14DWR2G
DescriptionIC CLOCK DISTRIB CHIP 1:5 20SOIC
ManufacturerON Semiconductor
Series100EL
TypeFanout Buffer (Distribution), Multiplexer
MC100EL14DWR2G datasheet
 


Specifications of MC100EL14DWR2G

Number Of Circuits1Ratio - Input:output2:5
Differential - Input:outputYes/YesInputECL, PECL
OutputECL, PECLFrequency - Max1GHz
Voltage - Supply4.2 V ~ 5.7 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case20-SOIC (7.5mm Width)
Frequency-max1GHzLead Free Status / RoHS StatusLead free / RoHS Compliant
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
Page 1/9

Download datasheet (137Kb)Embed
Next
MC100EL14
5V ECL 1:5 Clock
Distribution Chip
The MC100EL14 is a low skew 1:5 clock distribution chip designed
explicitly for low skew clock distribution applications. The V
internally generated voltage supply, is available to this device only.
For single-ended input conditions, the unused differential input is
connected to V
as a switching reference voltage. V
BB
rebias AC coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
should be left open.
BB
The EL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open and pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock
input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
Features
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
with V
= 0 V
EE
NECL Mode Operating Range: V
CC
with V
= −4.2 V to −5.7 V
EE
Q Output will Default LOW with Inputs Open or at V
Internal Input Pull−down Resistors on All Inputs, Pull−up Resistors
on Inverted Inputs
© Semiconductor Components Industries, LLC, 2008
November, 2008 − Rev. 8
pin, an
BB
may also
BB
and V
via a
BB
CC
= 4.2 V to 5.7 V
= 0 V
EE
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1
http://onsemi.com
SOIC−20L
DW SUFFIX
CASE 751D
MARKING DIAGRAM
20
100EL14
AWLYYWWG
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
Application Note AND8002/D.
ORDERING INFORMATION
Publication Order Number:
MC100EL14/D

MC100EL14DWR2G Summary of contents

  • Page 1

    MC100EL14 5V ECL 1:5 Clock Distribution Chip The MC100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The V internally generated voltage supply, is available to this device only. For single-ended input ...

  • Page 2

    ... Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 2 ...

  • Page 3

    SCLK CLK CLK All V pins are ...

  • Page 4

    Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

  • Page 5

    Table 5. 100EL SERIES PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

  • Page 6

    Table 7. AC CHARACTERISTICS V Symbol Characteristic f Maximum Toggle Frequency max (See Figure 2, f /Jitter) MAX t Prop CLK to Q (Diff) PLH t Delay CLK to Q (SE) PHL SCLK Part-to-Part Skew SKEW Within-Device ...

  • Page 7

    ... Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION4 Device MC100EL14DW MC100EL14DWG MC100EL14DWR2 MC100EL14DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

  • Page 8

    Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

  • Page 9

    ... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...