MC100EP14DTR2

Manufacturer Part NumberMC100EP14DTR2
DescriptionIC CLOCK DRVR 1:5 DIFF 20-TSSOP
ManufacturerON Semiconductor
Series100EP
TypeFanout Buffer (Distribution), Multiplexer
MC100EP14DTR2 datasheet
 


Specifications of MC100EP14DTR2

Number Of Circuits1Ratio - Input:output2:5
Differential - Input:outputYes/YesInputECL, HSTL, PECL
OutputECL, PECLFrequency - Max2GHz
Voltage - Supply3 V ~ 5.5 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case20-TSSOP
Frequency-max2GHzLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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MC100EP14
3.3V / 5V 1:5 Differential
ECL/PECL/HSTL Clock Driver
Description
The MC100EP14 is a low skew 1−to−5 differential driver, designed with
clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single−ended (if the V
output is used). HSTL inputs can be used when
BB
the LVEP14 is operating under PECL conditions.
The EP14 specifically guarantees low output−to−output skew. Optimal
design, layout, and processing minimize skew within a device and from
device to device.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
and V
via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V
should be left open.
BB
Features
400 ps Typical Propagation Delay
100 ps Device−to−Device Skew
25 ps Within Device Skew
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode:
V
= 3.0 V to 5.5 V with V
= 0 V
CC
EE
NECL Mode:
V
= 0 V with V
= −3.0 V to −5.5 V
CC
EE
Open Input Default State
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 6
as a switching reference voltage.
BB
1
http://onsemi.com
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
20
100
EP14
ALYWG
G
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
MC100EP14/D

MC100EP14DTR2 Summary of contents

  • Page 1

    MC100EP14 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential ...

  • Page 2

    WARNING: All V Figure 1. TSSOP−20 (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL ...

  • Page 3

    Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

  • Page 4

    Table 5. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

  • Page 5

    Table 7. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

  • Page 6

    ... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP14DT MC100EP14DTG MC100EP14DTR2 MC100EP14DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. 5.0 V 3.3 V É ...

  • Page 7

    Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

  • Page 8

    ... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...

  • Page 9

    ... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...